Sam Elliott 33c4407471 [RISCV] Support cR Inline Asm Constraint (#124174) ...

This denotes RVC-compatible GPR Pairs, which are used by the Zclsd
extension.

C API PR: riscv-non-isa/riscv-c-api-doc#102

2025-01-23 16:19:19 -08:00

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ntlh-intrinsics

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rvb-intrinsics

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rvk-intrinsics

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rvv-intrinsics-autogenerated

[clang][RISCV] Correct the SEW operand of indexed/fault only first segment intrinsics (#111476)

2024-10-15 07:40:37 -07:00

rvv-intrinsics-handcrafted

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__fp16-convert.c

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abi-empty-structs.c

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attr-hw-shadow-stack.c

[Clang][RISCV] Support -fcf-protection=return for RISC-V (#112477)

2024-10-29 15:47:49 +08:00

attr-riscv-rvv-vector-bits-less-8-call.c

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attr-riscv-rvv-vector-bits-less-8-cast.c

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attr-rvv-vector-bits-bitcast-less-8.c

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attr-rvv-vector-bits-bitcast.c

[Clang] Change two placeholders from undef to poison [NFC] (#119141)

2024-12-10 15:57:55 +00:00

attr-rvv-vector-bits-call.c

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attr-rvv-vector-bits-cast.c

[Clang] Change two placeholders from undef to poison [NFC] (#119141)

2024-12-10 15:57:55 +00:00

attr-rvv-vector-bits-codegen.c

[Clang] Change two placeholders from undef to poison [NFC] (#119141)

2024-12-10 15:57:55 +00:00

attr-rvv-vector-bits-globals.c

[Clang] Change two placeholders from undef to poison [NFC] (#119141)

2024-12-10 15:57:55 +00:00

attr-rvv-vector-bits-types.c

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bfloat-abi.c

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bfloat-mangle.cpp

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builtin-cpu-is-error.c

[RISCV] Support __builtin_cpu_is

2024-11-22 22:58:54 +08:00

builtin-cpu-is.c

[RISCV] Support __builtin_cpu_is

2024-11-22 22:58:54 +08:00

Float16-arith.c

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fpconstrained.c

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math-builtins.c

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riscv32-abi.c

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riscv32-ilp32d-abi.cpp

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riscv32-ilp32e-error.c

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riscv32-int128-abi.c

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riscv32-vararg.c

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riscv64-abi.c

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riscv64-vararg.c

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riscv-abi.cpp

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riscv-atomics.c

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riscv-attr-builtin-alias-err.c

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riscv-attr-builtin-alias.c

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riscv-cf-protection.c

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riscv-func-attr-target-err.c

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riscv-func-attr-target.c

[RISCV] Make A implies Zaamo and Zalrsc (#116907)

2024-11-22 10:35:38 +08:00

riscv-inline-asm-clobber.c

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riscv-inline-asm-rvv.c

[RISCV] Add support for inline asm constraint vd (#111653)

2024-10-14 10:47:59 +08:00

riscv-inline-asm.c

[RISCV] Support cR Inline Asm Constraint (#124174)

2025-01-23 16:19:19 -08:00

riscv-metadata-arch.c

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riscv-metadata.c

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riscv-sdata-module-flag.c

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riscv-v-debuginfo.c

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riscv-v-lifetime.cpp

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riscv-vector-callingconv-llvm-ir.c

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riscv-vector-callingconv-llvm-ir.cpp

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riscv-vector-callingconv.c

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riscv-vector-callingconv.cpp

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riscv-xcvalu-c-api.c

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riscv-xcvalu.c

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rvv-vls-arith-ops.c

[clang] Use poison instead of undef as the placeholder when creating a new vector [NFC] (#117064)

2024-12-02 09:00:39 +00:00

rvv-vls-bitwise-ops.c

[clang] Use poison instead of undef as the placeholder when creating a new vector [NFC] (#117064)

2024-12-02 09:00:39 +00:00

rvv-vls-compare-ops.c

[clang] Use poison instead of undef as the placeholder when creating a new vector [NFC] (#117064)

2024-12-02 09:00:39 +00:00

rvv-vls-shift-ops.c

[clang] Use poison instead of undef as the placeholder when creating a new vector [NFC] (#117064)

2024-12-02 09:00:39 +00:00

rvv-vls-subscript-ops.c

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tls-dialect.c

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vector-bits-vscale-range.c

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