7d5376270a
SearchableTable is the legacy version that does not appear to be well documented. Not sure if the plan was to delete it eventually. We can eventually use the PrimaryKey feature of GenericTable to remove one of the SearchIndex declarations. This will sort the generated table by the primary key and remove the separately generated indexing table to reduce .rodata size. This patch is just the mechanical migration. The size savings will be done in follow ups.
194 lines
4.3 KiB
C++
194 lines
4.3 KiB
C++
//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides basic encoding and assembly information for AArch64.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64BaseInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Regex.h"
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using namespace llvm;
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namespace llvm {
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namespace AArch64AT {
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#define GET_ATsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64DBnXS {
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#define GET_DBnXSsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64DB {
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#define GET_DBsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64DC {
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#define GET_DCsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64IC {
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#define GET_ICsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64ISB {
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#define GET_ISBsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64TSB {
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#define GET_TSBsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PRFM {
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#define GET_PRFMsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SVEPRFM {
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#define GET_SVEPRFMsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64RPRFM {
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#define GET_RPRFMsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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} // namespace AArch64RPRFM
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} // namespace llvm
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namespace llvm {
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namespace AArch64SVEPredPattern {
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#define GET_SVEPREDPATsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SVEVecLenSpecifier {
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#define GET_SVEVECLENSPECIFIERsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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} // namespace AArch64SVEVecLenSpecifier
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} // namespace llvm
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namespace llvm {
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namespace AArch64ExactFPImm {
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#define GET_ExactFPImmsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PState {
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#define GET_PStateImm0_15sList_IMPL
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#include "AArch64GenSystemOperands.inc"
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#define GET_PStateImm0_1sList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PSBHint {
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#define GET_PSBsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64PHint {
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#define GET_PHintsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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} // namespace AArch64PHint
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} // namespace llvm
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namespace llvm {
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namespace AArch64BTIHint {
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#define GET_BTIsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SysReg {
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#define GET_SysRegsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
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// Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
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static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
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std::string UpperName = Name.upper();
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SmallVector<StringRef, 5> Ops;
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if (!GenericRegPattern.match(UpperName, &Ops))
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return -1;
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uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
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uint32_t Bits;
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Ops[1].getAsInteger(10, Op0);
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Ops[2].getAsInteger(10, Op1);
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Ops[3].getAsInteger(10, CRn);
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Ops[4].getAsInteger(10, CRm);
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Ops[5].getAsInteger(10, Op2);
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Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
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return Bits;
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}
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std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
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assert(Bits < 0x10000);
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uint32_t Op0 = (Bits >> 14) & 0x3;
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uint32_t Op1 = (Bits >> 11) & 0x7;
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uint32_t CRn = (Bits >> 7) & 0xf;
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uint32_t CRm = (Bits >> 3) & 0xf;
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uint32_t Op2 = Bits & 0x7;
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return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
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utostr(CRm) + "_" + utostr(Op2);
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}
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namespace llvm {
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namespace AArch64TLBI {
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#define GET_TLBITable_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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namespace llvm {
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namespace AArch64SVCR {
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#define GET_SVCRsList_IMPL
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#include "AArch64GenSystemOperands.inc"
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}
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}
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