6206f5444f
Occupancy (i.e., the number of waves per EU) depends, in addition to register usage, on per-workgroup LDS usage as well as on the range of possible workgroup sizes. Mirroring the latter, occupancy should therefore be expressed as a range since different group sizes generally yield different achievable occupancies. `getOccupancyWithLocalMemSize` currently returns a scalar occupancy based on the maximum workgroup size and LDS usage. With respect to the workgroup size range, this scalar can be the minimum, the maximum, or neither of the two of the range of achievable occupancies. This commit fixes the function by making it compute and return the range of achievable occupancies w.r.t. workgroup size and LDS usage; it also renames it to `getOccupancyWithWorkGroupSizes` since it is the range of workgroup sizes that produces the range of achievable occupancies. Computing the achievable occupancy range is surprisingly involved. Minimum/maximum workgroup sizes do not necessarily yield maximum/minimum occupancies i.e., sometimes workgroup sizes inside the range yield the occupancy bounds. The implementation finds these sizes in constant time; heavy documentation explains the rationale behind the sometimes relatively obscure calculations. As a justifying example, consider a target with 10 waves / EU, 4 EUs/CU, 64-wide waves. Also consider a function with no LDS usage and a flat workgroup size range of [513,1024]. - A group of 513 items requires 9 waves per group. Only 4 groups made up of 9 waves each can fit fully on a CU at any given time, for a total of 36 waves on the CU, or 9 per EU. However, filling as much as possible the remaining 40-36=4 wave slots without decreasing the number of groups reveals that a larger group of 640 items yields 40 waves on the CU, or 10 per EU. - Similarly, a group of 1024 items requires 16 waves per group. Only 2 groups made up of 16 waves each can fit fully on a CU ay any given time, for a total of 32 waves on the CU, or 8 per EU. However, removing as many waves as possible from the groups without being able to fit another equal-sized group on the CU reveals that a smaller group of 896 items yields 28 waves on the CU, or 7 per EU. Therefore the achievable occupancy range for this function is not [8,9] as the group size bounds directly yield, but [7,10]. Naturally this change causes a lot of test churn as instruction scheduling is driven by achievable occupancy estimates. In most unit tests the flat workgroup size range is the default [1,1024] which, ignoring potential LDS limitations, would previously produce a scalar occupancy of 8 (derived from 1024) on a lot of targets, whereas we now consider the maximum occupancy to be 10 in such cases. Most tests are updated automatically and checked manually for sanity. I also manually changed some non-automatically generated assertions when necessary. Fixes #118220.
1752 lines
50 KiB
C++
1752 lines
50 KiB
C++
//=====-- GCNSubtarget.h - Define GCN Subtarget for AMDGPU ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// AMD GCN specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
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#define LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
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#include "AMDGPUCallLowering.h"
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#include "AMDGPURegisterBankInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIFrameLowering.h"
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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namespace llvm {
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class GCNTargetMachine;
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class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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public AMDGPUSubtarget {
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public:
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using AMDGPUSubtarget::getMaxWavesPerEU;
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// Following 2 enums are documented at:
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// - https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi
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enum class TrapHandlerAbi {
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NONE = 0x00,
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AMDHSA = 0x01,
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};
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enum class TrapID {
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LLVMAMDHSATrap = 0x02,
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LLVMAMDHSADebugTrap = 0x03,
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};
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private:
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/// SelectionDAGISel related APIs.
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std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
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std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<AMDGPURegisterBankInfo> RegBankInfo;
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protected:
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// Basic subtarget description.
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Triple TargetTriple;
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AMDGPU::IsaInfo::AMDGPUTargetID TargetID;
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unsigned Gen = INVALID;
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InstrItineraryData InstrItins;
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int LDSBankCount = 0;
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unsigned MaxPrivateElementSize = 0;
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// Possibly statically set by tablegen, but may want to be overridden.
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bool FastDenormalF32 = false;
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bool HalfRate64Ops = false;
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bool FullRate64Ops = false;
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// Dynamically set bits that enable features.
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bool FlatForGlobal = false;
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bool AutoWaitcntBeforeBarrier = false;
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bool BackOffBarrier = false;
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bool UnalignedScratchAccess = false;
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bool UnalignedAccessMode = false;
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bool HasApertureRegs = false;
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bool SupportsXNACK = false;
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bool KernargPreload = false;
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// This should not be used directly. 'TargetID' tracks the dynamic settings
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// for XNACK.
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bool EnableXNACK = false;
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bool EnableTgSplit = false;
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bool EnableCuMode = false;
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bool TrapHandler = false;
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bool EnablePreciseMemory = false;
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// Used as options.
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bool EnableLoadStoreOpt = false;
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bool EnableUnsafeDSOffsetFolding = false;
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bool EnableSIScheduler = false;
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bool EnableDS128 = false;
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bool EnablePRTStrictNull = false;
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bool DumpCode = false;
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// Subtarget statically properties set by tablegen
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bool FP64 = false;
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bool FMA = false;
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bool MIMG_R128 = false;
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bool CIInsts = false;
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bool GFX8Insts = false;
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bool GFX9Insts = false;
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bool GFX90AInsts = false;
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bool GFX940Insts = false;
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bool GFX950Insts = false;
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bool GFX10Insts = false;
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bool GFX11Insts = false;
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bool GFX12Insts = false;
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bool GFX10_3Insts = false;
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bool GFX7GFX8GFX9Insts = false;
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bool SGPRInitBug = false;
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bool UserSGPRInit16Bug = false;
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bool NegativeScratchOffsetBug = false;
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bool NegativeUnalignedScratchOffsetBug = false;
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bool HasSMemRealTime = false;
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bool HasIntClamp = false;
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bool HasFmaMixInsts = false;
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bool HasMovrel = false;
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bool HasVGPRIndexMode = false;
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bool HasScalarDwordx3Loads = false;
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bool HasScalarStores = false;
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bool HasScalarAtomics = false;
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bool HasSDWAOmod = false;
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bool HasSDWAScalar = false;
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bool HasSDWASdst = false;
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bool HasSDWAMac = false;
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bool HasSDWAOutModsVOPC = false;
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bool HasDPP = false;
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bool HasDPP8 = false;
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bool HasDPALU_DPP = false;
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bool HasDPPSrc1SGPR = false;
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bool HasPackedFP32Ops = false;
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bool HasImageInsts = false;
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bool HasExtendedImageInsts = false;
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bool HasR128A16 = false;
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bool HasA16 = false;
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bool HasG16 = false;
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bool HasNSAEncoding = false;
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bool HasPartialNSAEncoding = false;
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bool GFX10_AEncoding = false;
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bool GFX10_BEncoding = false;
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bool HasDLInsts = false;
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bool HasFmacF64Inst = false;
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bool HasDot1Insts = false;
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bool HasDot2Insts = false;
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bool HasDot3Insts = false;
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bool HasDot4Insts = false;
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bool HasDot5Insts = false;
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bool HasDot6Insts = false;
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bool HasDot7Insts = false;
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bool HasDot8Insts = false;
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bool HasDot9Insts = false;
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bool HasDot10Insts = false;
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bool HasDot11Insts = false;
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bool HasDot12Insts = false;
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bool HasDot13Insts = false;
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bool HasMAIInsts = false;
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bool HasFP8Insts = false;
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bool HasFP8ConversionInsts = false;
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bool HasCvtFP8Vop1Bug = false;
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bool HasPkFmacF16Inst = false;
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bool HasAtomicFMinFMaxF32GlobalInsts = false;
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bool HasAtomicFMinFMaxF64GlobalInsts = false;
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bool HasAtomicFMinFMaxF32FlatInsts = false;
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bool HasAtomicFMinFMaxF64FlatInsts = false;
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bool HasAtomicDsPkAdd16Insts = false;
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bool HasAtomicFlatPkAdd16Insts = false;
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bool HasAtomicFaddRtnInsts = false;
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bool HasAtomicFaddNoRtnInsts = false;
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bool HasMemoryAtomicFaddF32DenormalSupport = false;
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bool HasAtomicBufferGlobalPkAddF16NoRtnInsts = false;
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bool HasAtomicBufferGlobalPkAddF16Insts = false;
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bool HasAtomicCSubNoRtnInsts = false;
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bool HasAtomicGlobalPkAddBF16Inst = false;
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bool HasAtomicBufferPkAddBF16Inst = false;
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bool HasFlatAtomicFaddF32Inst = false;
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bool HasFlatBufferGlobalAtomicFaddF64Inst = false;
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bool HasDefaultComponentZero = false;
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bool HasAgentScopeFineGrainedRemoteMemoryAtomics = false;
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bool HasDefaultComponentBroadcast = false;
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bool HasXF32Insts = false;
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/// The maximum number of instructions that may be placed within an S_CLAUSE,
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/// which is one greater than the maximum argument to S_CLAUSE. A value of 0
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/// indicates a lack of S_CLAUSE support.
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unsigned MaxHardClauseLength = 0;
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bool SupportsSRAMECC = false;
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// This should not be used directly. 'TargetID' tracks the dynamic settings
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// for SRAMECC.
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bool EnableSRAMECC = false;
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bool HasNoSdstCMPX = false;
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bool HasVscnt = false;
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bool HasGetWaveIdInst = false;
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bool HasSMemTimeInst = false;
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bool HasShaderCyclesRegister = false;
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bool HasShaderCyclesHiLoRegisters = false;
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bool HasVOP3Literal = false;
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bool HasNoDataDepHazard = false;
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bool FlatAddressSpace = false;
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bool FlatInstOffsets = false;
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bool FlatGlobalInsts = false;
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bool FlatScratchInsts = false;
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bool ScalarFlatScratchInsts = false;
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bool HasArchitectedFlatScratch = false;
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bool EnableFlatScratch = false;
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bool HasArchitectedSGPRs = false;
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bool HasGDS = false;
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bool HasGWS = false;
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bool AddNoCarryInsts = false;
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bool HasUnpackedD16VMem = false;
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bool LDSMisalignedBug = false;
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bool HasMFMAInlineLiteralBug = false;
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bool UnalignedBufferAccess = false;
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bool UnalignedDSAccess = false;
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bool HasPackedTID = false;
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bool ScalarizeGlobal = false;
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bool HasSALUFloatInsts = false;
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bool HasPseudoScalarTrans = false;
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bool HasRestrictedSOffset = false;
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bool HasBitOp3Insts = false;
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bool HasPrngInst = false;
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bool HasPermlane16Swap = false;
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bool HasPermlane32Swap = false;
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bool HasVcmpxPermlaneHazard = false;
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bool HasVMEMtoScalarWriteHazard = false;
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bool HasSMEMtoVectorWriteHazard = false;
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bool HasInstFwdPrefetchBug = false;
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bool HasVcmpxExecWARHazard = false;
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bool HasLdsBranchVmemWARHazard = false;
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bool HasNSAtoVMEMBug = false;
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bool HasNSAClauseBug = false;
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bool HasOffset3fBug = false;
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bool HasFlatSegmentOffsetBug = false;
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bool HasImageStoreD16Bug = false;
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bool HasImageGather4D16Bug = false;
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bool HasMSAALoadDstSelBug = false;
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bool HasPrivEnabledTrap2NopBug = false;
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bool Has1_5xVGPRs = false;
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bool HasMADIntraFwdBug = false;
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bool HasVOPDInsts = false;
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bool HasVALUTransUseHazard = false;
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bool HasForceStoreSC0SC1 = false;
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bool HasRequiredExportPriority = false;
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bool HasVmemWriteVgprInOrder = false;
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bool HasAshrPkInsts = false;
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bool HasMinimum3Maximum3F32 = false;
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bool HasMinimum3Maximum3F16 = false;
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bool HasMinimum3Maximum3PKF16 = false;
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bool RequiresCOV6 = false;
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// Dummy feature to use for assembler in tablegen.
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bool FeatureDisable = false;
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private:
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SIInstrInfo InstrInfo;
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SITargetLowering TLInfo;
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SIFrameLowering FrameLowering;
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public:
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GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const GCNTargetMachine &TM);
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~GCNSubtarget() override;
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GCNSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef GPU, StringRef FS);
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/// Diagnose inconsistent subtarget features before attempting to codegen
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/// function \p F.
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void checkSubtargetFeatures(const Function &F) const;
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const SIInstrInfo *getInstrInfo() const override {
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return &InstrInfo;
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}
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const SIFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const SITargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SIRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
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const CallLowering *getCallLowering() const override {
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return CallLoweringInfo.get();
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}
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const InlineAsmLowering *getInlineAsmLowering() const override {
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return InlineAsmLoweringInfo.get();
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}
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InstructionSelector *getInstructionSelector() const override {
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return InstSelector.get();
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}
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const LegalizerInfo *getLegalizerInfo() const override {
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return Legalizer.get();
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}
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const AMDGPURegisterBankInfo *getRegBankInfo() const override {
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return RegBankInfo.get();
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}
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const AMDGPU::IsaInfo::AMDGPUTargetID &getTargetID() const {
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return TargetID;
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}
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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Generation getGeneration() const {
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return (Generation)Gen;
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}
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unsigned getMaxWaveScratchSize() const {
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// See COMPUTE_TMPRING_SIZE.WAVESIZE.
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if (getGeneration() >= GFX12) {
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// 18-bit field in units of 64-dword.
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return (64 * 4) * ((1 << 18) - 1);
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}
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if (getGeneration() == GFX11) {
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// 15-bit field in units of 64-dword.
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return (64 * 4) * ((1 << 15) - 1);
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}
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// 13-bit field in units of 256-dword.
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return (256 * 4) * ((1 << 13) - 1);
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}
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/// Return the number of high bits known to be zero for a frame index.
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unsigned getKnownHighZeroBitsForFrameIndex() const {
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return llvm::countl_zero(getMaxWaveScratchSize()) + getWavefrontSizeLog2();
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}
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int getLDSBankCount() const {
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return LDSBankCount;
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}
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unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
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return (ForBufferRSrc || !enableFlatScratch()) ? MaxPrivateElementSize : 16;
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}
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unsigned getConstantBusLimit(unsigned Opcode) const;
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/// Returns if the result of this instruction with a 16-bit result returned in
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/// a 32-bit register implicitly zeroes the high 16-bits, rather than preserve
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/// the original value.
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bool zeroesHigh16BitsOfDest(unsigned Opcode) const;
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bool supportsWGP() const { return getGeneration() >= GFX10; }
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bool hasIntClamp() const {
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return HasIntClamp;
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}
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bool hasFP64() const {
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return FP64;
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}
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bool hasMIMG_R128() const {
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return MIMG_R128;
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}
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bool hasHWFP64() const {
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return FP64;
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}
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bool hasHalfRate64Ops() const {
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return HalfRate64Ops;
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}
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bool hasFullRate64Ops() const {
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return FullRate64Ops;
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}
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bool hasAddr64() const {
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return (getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS);
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}
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bool hasFlat() const {
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return (getGeneration() > AMDGPUSubtarget::SOUTHERN_ISLANDS);
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}
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// Return true if the target only has the reverse operand versions of VALU
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// shift instructions (e.g. v_lshrrev_b32, and no v_lshr_b32).
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bool hasOnlyRevVALUShifts() const {
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return getGeneration() >= VOLCANIC_ISLANDS;
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}
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bool hasFractBug() const {
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return getGeneration() == SOUTHERN_ISLANDS;
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}
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bool hasBFE() const {
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return true;
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}
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bool hasBFI() const {
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return true;
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}
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bool hasBFM() const {
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return hasBFE();
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}
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bool hasBCNT(unsigned Size) const {
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return true;
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}
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bool hasFFBL() const {
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return true;
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}
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bool hasFFBH() const {
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return true;
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}
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bool hasMed3_16() const {
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return getGeneration() >= AMDGPUSubtarget::GFX9;
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}
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bool hasMin3Max3_16() const {
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return getGeneration() >= AMDGPUSubtarget::GFX9;
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}
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bool hasFmaMixInsts() const {
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return HasFmaMixInsts;
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}
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bool hasCARRY() const {
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return true;
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}
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bool hasFMA() const {
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return FMA;
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}
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bool hasSwap() const {
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return GFX9Insts;
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}
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bool hasScalarPackInsts() const {
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return GFX9Insts;
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}
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bool hasScalarMulHiInsts() const {
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return GFX9Insts;
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}
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bool hasScalarSubwordLoads() const { return getGeneration() >= GFX12; }
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TrapHandlerAbi getTrapHandlerAbi() const {
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return isAmdHsaOS() ? TrapHandlerAbi::AMDHSA : TrapHandlerAbi::NONE;
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}
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bool supportsGetDoorbellID() const {
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// The S_GETREG DOORBELL_ID is supported by all GFX9 onward targets.
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return getGeneration() >= GFX9;
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}
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/// True if the offset field of DS instructions works as expected. On SI, the
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/// offset uses a 16-bit adder and does not always wrap properly.
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bool hasUsableDSOffset() const {
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return getGeneration() >= SEA_ISLANDS;
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}
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bool unsafeDSOffsetFoldingEnabled() const {
|
|
return EnableUnsafeDSOffsetFolding;
|
|
}
|
|
|
|
/// Condition output from div_scale is usable.
|
|
bool hasUsableDivScaleConditionOutput() const {
|
|
return getGeneration() != SOUTHERN_ISLANDS;
|
|
}
|
|
|
|
/// Extra wait hazard is needed in some cases before
|
|
/// s_cbranch_vccnz/s_cbranch_vccz.
|
|
bool hasReadVCCZBug() const {
|
|
return getGeneration() <= SEA_ISLANDS;
|
|
}
|
|
|
|
/// Writes to VCC_LO/VCC_HI update the VCCZ flag.
|
|
bool partialVCCWritesUpdateVCCZ() const {
|
|
return getGeneration() >= GFX10;
|
|
}
|
|
|
|
/// A read of an SGPR by SMRD instruction requires 4 wait states when the SGPR
|
|
/// was written by a VALU instruction.
|
|
bool hasSMRDReadVALUDefHazard() const {
|
|
return getGeneration() == SOUTHERN_ISLANDS;
|
|
}
|
|
|
|
/// A read of an SGPR by a VMEM instruction requires 5 wait states when the
|
|
/// SGPR was written by a VALU Instruction.
|
|
bool hasVMEMReadSGPRVALUDefHazard() const {
|
|
return getGeneration() >= VOLCANIC_ISLANDS;
|
|
}
|
|
|
|
bool hasRFEHazards() const {
|
|
return getGeneration() >= VOLCANIC_ISLANDS;
|
|
}
|
|
|
|
/// Number of hazard wait states for s_setreg_b32/s_setreg_imm32_b32.
|
|
unsigned getSetRegWaitStates() const {
|
|
return getGeneration() <= SEA_ISLANDS ? 1 : 2;
|
|
}
|
|
|
|
bool dumpCode() const {
|
|
return DumpCode;
|
|
}
|
|
|
|
/// Return the amount of LDS that can be used that will not restrict the
|
|
/// occupancy lower than WaveCount.
|
|
unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
|
|
const Function &) const;
|
|
|
|
bool supportsMinMaxDenormModes() const {
|
|
return getGeneration() >= AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
/// \returns If target supports S_DENORM_MODE.
|
|
bool hasDenormModeInst() const {
|
|
return getGeneration() >= AMDGPUSubtarget::GFX10;
|
|
}
|
|
|
|
bool useFlatForGlobal() const {
|
|
return FlatForGlobal;
|
|
}
|
|
|
|
/// \returns If target supports ds_read/write_b128 and user enables generation
|
|
/// of ds_read/write_b128.
|
|
bool useDS128() const {
|
|
return CIInsts && EnableDS128;
|
|
}
|
|
|
|
/// \return If target supports ds_read/write_b96/128.
|
|
bool hasDS96AndDS128() const {
|
|
return CIInsts;
|
|
}
|
|
|
|
/// Have v_trunc_f64, v_ceil_f64, v_rndne_f64
|
|
bool haveRoundOpsF64() const {
|
|
return CIInsts;
|
|
}
|
|
|
|
/// \returns If MUBUF instructions always perform range checking, even for
|
|
/// buffer resources used for private memory access.
|
|
bool privateMemoryResourceIsRangeChecked() const {
|
|
return getGeneration() < AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
/// \returns If target requires PRT Struct NULL support (zero result registers
|
|
/// for sparse texture support).
|
|
bool usePRTStrictNull() const {
|
|
return EnablePRTStrictNull;
|
|
}
|
|
|
|
bool hasAutoWaitcntBeforeBarrier() const {
|
|
return AutoWaitcntBeforeBarrier;
|
|
}
|
|
|
|
/// \returns true if the target supports backing off of s_barrier instructions
|
|
/// when an exception is raised.
|
|
bool supportsBackOffBarrier() const {
|
|
return BackOffBarrier;
|
|
}
|
|
|
|
bool hasUnalignedBufferAccess() const {
|
|
return UnalignedBufferAccess;
|
|
}
|
|
|
|
bool hasUnalignedBufferAccessEnabled() const {
|
|
return UnalignedBufferAccess && UnalignedAccessMode;
|
|
}
|
|
|
|
bool hasUnalignedDSAccess() const {
|
|
return UnalignedDSAccess;
|
|
}
|
|
|
|
bool hasUnalignedDSAccessEnabled() const {
|
|
return UnalignedDSAccess && UnalignedAccessMode;
|
|
}
|
|
|
|
bool hasUnalignedScratchAccess() const {
|
|
return UnalignedScratchAccess;
|
|
}
|
|
|
|
bool hasUnalignedScratchAccessEnabled() const {
|
|
return UnalignedScratchAccess && UnalignedAccessMode;
|
|
}
|
|
|
|
bool hasUnalignedAccessMode() const {
|
|
return UnalignedAccessMode;
|
|
}
|
|
|
|
bool hasApertureRegs() const {
|
|
return HasApertureRegs;
|
|
}
|
|
|
|
bool isTrapHandlerEnabled() const {
|
|
return TrapHandler;
|
|
}
|
|
|
|
bool isXNACKEnabled() const {
|
|
return TargetID.isXnackOnOrAny();
|
|
}
|
|
|
|
bool isTgSplitEnabled() const {
|
|
return EnableTgSplit;
|
|
}
|
|
|
|
bool isCuModeEnabled() const {
|
|
return EnableCuMode;
|
|
}
|
|
|
|
bool isPreciseMemoryEnabled() const { return EnablePreciseMemory; }
|
|
|
|
bool hasFlatAddressSpace() const {
|
|
return FlatAddressSpace;
|
|
}
|
|
|
|
bool hasFlatScrRegister() const {
|
|
return hasFlatAddressSpace();
|
|
}
|
|
|
|
bool hasFlatInstOffsets() const {
|
|
return FlatInstOffsets;
|
|
}
|
|
|
|
bool hasFlatGlobalInsts() const {
|
|
return FlatGlobalInsts;
|
|
}
|
|
|
|
bool hasFlatScratchInsts() const {
|
|
return FlatScratchInsts;
|
|
}
|
|
|
|
// Check if target supports ST addressing mode with FLAT scratch instructions.
|
|
// The ST addressing mode means no registers are used, either VGPR or SGPR,
|
|
// but only immediate offset is swizzled and added to the FLAT scratch base.
|
|
bool hasFlatScratchSTMode() const {
|
|
return hasFlatScratchInsts() && (hasGFX10_3Insts() || hasGFX940Insts());
|
|
}
|
|
|
|
bool hasFlatScratchSVSMode() const { return GFX940Insts || GFX11Insts; }
|
|
|
|
bool hasScalarFlatScratchInsts() const {
|
|
return ScalarFlatScratchInsts;
|
|
}
|
|
|
|
bool enableFlatScratch() const {
|
|
return flatScratchIsArchitected() ||
|
|
(EnableFlatScratch && hasFlatScratchInsts());
|
|
}
|
|
|
|
bool hasGlobalAddTidInsts() const {
|
|
return GFX10_BEncoding;
|
|
}
|
|
|
|
bool hasAtomicCSub() const {
|
|
return GFX10_BEncoding;
|
|
}
|
|
|
|
bool hasExportInsts() const {
|
|
return !hasGFX940Insts();
|
|
}
|
|
|
|
bool hasVINTERPEncoding() const {
|
|
return GFX11Insts;
|
|
}
|
|
|
|
// DS_ADD_F64/DS_ADD_RTN_F64
|
|
bool hasLdsAtomicAddF64() const { return hasGFX90AInsts(); }
|
|
|
|
bool hasMultiDwordFlatScratchAddressing() const {
|
|
return getGeneration() >= GFX9;
|
|
}
|
|
|
|
bool hasFlatSegmentOffsetBug() const {
|
|
return HasFlatSegmentOffsetBug;
|
|
}
|
|
|
|
bool hasFlatLgkmVMemCountInOrder() const {
|
|
return getGeneration() > GFX9;
|
|
}
|
|
|
|
bool hasD16LoadStore() const {
|
|
return getGeneration() >= GFX9;
|
|
}
|
|
|
|
bool d16PreservesUnusedBits() const {
|
|
return hasD16LoadStore() && !TargetID.isSramEccOnOrAny();
|
|
}
|
|
|
|
bool hasD16Images() const {
|
|
return getGeneration() >= VOLCANIC_ISLANDS;
|
|
}
|
|
|
|
/// Return if most LDS instructions have an m0 use that require m0 to be
|
|
/// initialized.
|
|
bool ldsRequiresM0Init() const {
|
|
return getGeneration() < GFX9;
|
|
}
|
|
|
|
// True if the hardware rewinds and replays GWS operations if a wave is
|
|
// preempted.
|
|
//
|
|
// If this is false, a GWS operation requires testing if a nack set the
|
|
// MEM_VIOL bit, and repeating if so.
|
|
bool hasGWSAutoReplay() const {
|
|
return getGeneration() >= GFX9;
|
|
}
|
|
|
|
/// \returns if target has ds_gws_sema_release_all instruction.
|
|
bool hasGWSSemaReleaseAll() const {
|
|
return CIInsts;
|
|
}
|
|
|
|
/// \returns true if the target has integer add/sub instructions that do not
|
|
/// produce a carry-out. This includes v_add_[iu]32, v_sub_[iu]32,
|
|
/// v_add_[iu]16, and v_sub_[iu]16, all of which support the clamp modifier
|
|
/// for saturation.
|
|
bool hasAddNoCarry() const {
|
|
return AddNoCarryInsts;
|
|
}
|
|
|
|
bool hasScalarAddSub64() const { return getGeneration() >= GFX12; }
|
|
|
|
bool hasScalarSMulU64() const { return getGeneration() >= GFX12; }
|
|
|
|
bool hasUnpackedD16VMem() const {
|
|
return HasUnpackedD16VMem;
|
|
}
|
|
|
|
// Covers VS/PS/CS graphics shaders
|
|
bool isMesaGfxShader(const Function &F) const {
|
|
return isMesa3DOS() && AMDGPU::isShader(F.getCallingConv());
|
|
}
|
|
|
|
bool hasMad64_32() const {
|
|
return getGeneration() >= SEA_ISLANDS;
|
|
}
|
|
|
|
bool hasSDWAOmod() const {
|
|
return HasSDWAOmod;
|
|
}
|
|
|
|
bool hasSDWAScalar() const {
|
|
return HasSDWAScalar;
|
|
}
|
|
|
|
bool hasSDWASdst() const {
|
|
return HasSDWASdst;
|
|
}
|
|
|
|
bool hasSDWAMac() const {
|
|
return HasSDWAMac;
|
|
}
|
|
|
|
bool hasSDWAOutModsVOPC() const {
|
|
return HasSDWAOutModsVOPC;
|
|
}
|
|
|
|
bool hasDLInsts() const {
|
|
return HasDLInsts;
|
|
}
|
|
|
|
bool hasFmacF64Inst() const { return HasFmacF64Inst; }
|
|
|
|
bool hasDot1Insts() const {
|
|
return HasDot1Insts;
|
|
}
|
|
|
|
bool hasDot2Insts() const {
|
|
return HasDot2Insts;
|
|
}
|
|
|
|
bool hasDot3Insts() const {
|
|
return HasDot3Insts;
|
|
}
|
|
|
|
bool hasDot4Insts() const {
|
|
return HasDot4Insts;
|
|
}
|
|
|
|
bool hasDot5Insts() const {
|
|
return HasDot5Insts;
|
|
}
|
|
|
|
bool hasDot6Insts() const {
|
|
return HasDot6Insts;
|
|
}
|
|
|
|
bool hasDot7Insts() const {
|
|
return HasDot7Insts;
|
|
}
|
|
|
|
bool hasDot8Insts() const {
|
|
return HasDot8Insts;
|
|
}
|
|
|
|
bool hasDot9Insts() const {
|
|
return HasDot9Insts;
|
|
}
|
|
|
|
bool hasDot10Insts() const {
|
|
return HasDot10Insts;
|
|
}
|
|
|
|
bool hasDot11Insts() const {
|
|
return HasDot11Insts;
|
|
}
|
|
|
|
bool hasDot12Insts() const {
|
|
return HasDot12Insts;
|
|
}
|
|
|
|
bool hasDot13Insts() const {
|
|
return HasDot13Insts;
|
|
}
|
|
|
|
bool hasMAIInsts() const {
|
|
return HasMAIInsts;
|
|
}
|
|
|
|
bool hasFP8Insts() const {
|
|
return HasFP8Insts;
|
|
}
|
|
|
|
bool hasFP8ConversionInsts() const { return HasFP8ConversionInsts; }
|
|
|
|
bool hasPkFmacF16Inst() const {
|
|
return HasPkFmacF16Inst;
|
|
}
|
|
|
|
bool hasAtomicFMinFMaxF32GlobalInsts() const {
|
|
return HasAtomicFMinFMaxF32GlobalInsts;
|
|
}
|
|
|
|
bool hasAtomicFMinFMaxF64GlobalInsts() const {
|
|
return HasAtomicFMinFMaxF64GlobalInsts;
|
|
}
|
|
|
|
bool hasAtomicFMinFMaxF32FlatInsts() const {
|
|
return HasAtomicFMinFMaxF32FlatInsts;
|
|
}
|
|
|
|
bool hasAtomicFMinFMaxF64FlatInsts() const {
|
|
return HasAtomicFMinFMaxF64FlatInsts;
|
|
}
|
|
|
|
bool hasAtomicDsPkAdd16Insts() const { return HasAtomicDsPkAdd16Insts; }
|
|
|
|
bool hasAtomicFlatPkAdd16Insts() const { return HasAtomicFlatPkAdd16Insts; }
|
|
|
|
bool hasAtomicFaddInsts() const {
|
|
return HasAtomicFaddRtnInsts || HasAtomicFaddNoRtnInsts;
|
|
}
|
|
|
|
bool hasAtomicFaddRtnInsts() const { return HasAtomicFaddRtnInsts; }
|
|
|
|
bool hasAtomicFaddNoRtnInsts() const { return HasAtomicFaddNoRtnInsts; }
|
|
|
|
bool hasAtomicBufferGlobalPkAddF16NoRtnInsts() const {
|
|
return HasAtomicBufferGlobalPkAddF16NoRtnInsts;
|
|
}
|
|
|
|
bool hasAtomicBufferGlobalPkAddF16Insts() const {
|
|
return HasAtomicBufferGlobalPkAddF16Insts;
|
|
}
|
|
|
|
bool hasAtomicGlobalPkAddBF16Inst() const {
|
|
return HasAtomicGlobalPkAddBF16Inst;
|
|
}
|
|
|
|
bool hasAtomicBufferPkAddBF16Inst() const {
|
|
return HasAtomicBufferPkAddBF16Inst;
|
|
}
|
|
|
|
bool hasFlatAtomicFaddF32Inst() const { return HasFlatAtomicFaddF32Inst; }
|
|
|
|
/// \return true if the target has flat, global, and buffer atomic fadd for
|
|
/// double.
|
|
bool hasFlatBufferGlobalAtomicFaddF64Inst() const {
|
|
return HasFlatBufferGlobalAtomicFaddF64Inst;
|
|
}
|
|
|
|
/// \return true if the target's flat, global, and buffer atomic fadd for
|
|
/// float supports denormal handling.
|
|
bool hasMemoryAtomicFaddF32DenormalSupport() const {
|
|
return HasMemoryAtomicFaddF32DenormalSupport;
|
|
}
|
|
|
|
/// \return true if atomic operations targeting fine-grained memory work
|
|
/// correctly at device scope, in allocations in host or peer PCIe device
|
|
/// memory.
|
|
bool supportsAgentScopeFineGrainedRemoteMemoryAtomics() const {
|
|
return HasAgentScopeFineGrainedRemoteMemoryAtomics;
|
|
}
|
|
|
|
bool hasDefaultComponentZero() const { return HasDefaultComponentZero; }
|
|
|
|
bool hasDefaultComponentBroadcast() const {
|
|
return HasDefaultComponentBroadcast;
|
|
}
|
|
|
|
bool hasNoSdstCMPX() const {
|
|
return HasNoSdstCMPX;
|
|
}
|
|
|
|
bool hasVscnt() const {
|
|
return HasVscnt;
|
|
}
|
|
|
|
bool hasGetWaveIdInst() const {
|
|
return HasGetWaveIdInst;
|
|
}
|
|
|
|
bool hasSMemTimeInst() const {
|
|
return HasSMemTimeInst;
|
|
}
|
|
|
|
bool hasShaderCyclesRegister() const {
|
|
return HasShaderCyclesRegister;
|
|
}
|
|
|
|
bool hasShaderCyclesHiLoRegisters() const {
|
|
return HasShaderCyclesHiLoRegisters;
|
|
}
|
|
|
|
bool hasVOP3Literal() const {
|
|
return HasVOP3Literal;
|
|
}
|
|
|
|
bool hasNoDataDepHazard() const {
|
|
return HasNoDataDepHazard;
|
|
}
|
|
|
|
bool vmemWriteNeedsExpWaitcnt() const {
|
|
return getGeneration() < SEA_ISLANDS;
|
|
}
|
|
|
|
bool hasInstPrefetch() const {
|
|
return getGeneration() == GFX10 || getGeneration() == GFX11;
|
|
}
|
|
|
|
bool hasPrefetch() const { return GFX12Insts; }
|
|
|
|
// Has s_cmpk_* instructions.
|
|
bool hasSCmpK() const { return getGeneration() < GFX12; }
|
|
|
|
// Scratch is allocated in 256 dword per wave blocks for the entire
|
|
// wavefront. When viewed from the perspective of an arbitrary workitem, this
|
|
// is 4-byte aligned.
|
|
//
|
|
// Only 4-byte alignment is really needed to access anything. Transformations
|
|
// on the pointer value itself may rely on the alignment / known low bits of
|
|
// the pointer. Set this to something above the minimum to avoid needing
|
|
// dynamic realignment in common cases.
|
|
Align getStackAlignment() const { return Align(16); }
|
|
|
|
bool enableMachineScheduler() const override {
|
|
return true;
|
|
}
|
|
|
|
bool useAA() const override;
|
|
|
|
bool enableSubRegLiveness() const override {
|
|
return true;
|
|
}
|
|
|
|
void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b; }
|
|
bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal; }
|
|
|
|
// static wrappers
|
|
static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
|
|
|
|
// XXX - Why is this here if it isn't in the default pass set?
|
|
bool enableEarlyIfConversion() const override {
|
|
return true;
|
|
}
|
|
|
|
void overrideSchedPolicy(MachineSchedPolicy &Policy,
|
|
unsigned NumRegionInstrs) const override;
|
|
|
|
void mirFileLoaded(MachineFunction &MF) const override;
|
|
|
|
unsigned getMaxNumUserSGPRs() const {
|
|
return AMDGPU::getMaxNumUserSGPRs(*this);
|
|
}
|
|
|
|
bool hasSMemRealTime() const {
|
|
return HasSMemRealTime;
|
|
}
|
|
|
|
bool hasMovrel() const {
|
|
return HasMovrel;
|
|
}
|
|
|
|
bool hasVGPRIndexMode() const {
|
|
return HasVGPRIndexMode;
|
|
}
|
|
|
|
bool useVGPRIndexMode() const;
|
|
|
|
bool hasScalarCompareEq64() const {
|
|
return getGeneration() >= VOLCANIC_ISLANDS;
|
|
}
|
|
|
|
bool hasScalarDwordx3Loads() const { return HasScalarDwordx3Loads; }
|
|
|
|
bool hasScalarStores() const {
|
|
return HasScalarStores;
|
|
}
|
|
|
|
bool hasScalarAtomics() const {
|
|
return HasScalarAtomics;
|
|
}
|
|
|
|
bool hasLDSFPAtomicAddF32() const { return GFX8Insts; }
|
|
bool hasLDSFPAtomicAddF64() const { return GFX90AInsts; }
|
|
|
|
/// \returns true if the subtarget has the v_permlanex16_b32 instruction.
|
|
bool hasPermLaneX16() const { return getGeneration() >= GFX10; }
|
|
|
|
/// \returns true if the subtarget has the v_permlane64_b32 instruction.
|
|
bool hasPermLane64() const { return getGeneration() >= GFX11; }
|
|
|
|
bool hasDPP() const {
|
|
return HasDPP;
|
|
}
|
|
|
|
bool hasDPPBroadcasts() const {
|
|
return HasDPP && getGeneration() < GFX10;
|
|
}
|
|
|
|
bool hasDPPWavefrontShifts() const {
|
|
return HasDPP && getGeneration() < GFX10;
|
|
}
|
|
|
|
bool hasDPP8() const {
|
|
return HasDPP8;
|
|
}
|
|
|
|
bool hasDPALU_DPP() const {
|
|
return HasDPALU_DPP;
|
|
}
|
|
|
|
bool hasDPPSrc1SGPR() const { return HasDPPSrc1SGPR; }
|
|
|
|
bool hasPackedFP32Ops() const {
|
|
return HasPackedFP32Ops;
|
|
}
|
|
|
|
// Has V_PK_MOV_B32 opcode
|
|
bool hasPkMovB32() const {
|
|
return GFX90AInsts;
|
|
}
|
|
|
|
bool hasFmaakFmamkF32Insts() const {
|
|
return getGeneration() >= GFX10 || hasGFX940Insts();
|
|
}
|
|
|
|
bool hasImageInsts() const {
|
|
return HasImageInsts;
|
|
}
|
|
|
|
bool hasExtendedImageInsts() const {
|
|
return HasExtendedImageInsts;
|
|
}
|
|
|
|
bool hasR128A16() const {
|
|
return HasR128A16;
|
|
}
|
|
|
|
bool hasA16() const { return HasA16; }
|
|
|
|
bool hasG16() const { return HasG16; }
|
|
|
|
bool hasOffset3fBug() const {
|
|
return HasOffset3fBug;
|
|
}
|
|
|
|
bool hasImageStoreD16Bug() const { return HasImageStoreD16Bug; }
|
|
|
|
bool hasImageGather4D16Bug() const { return HasImageGather4D16Bug; }
|
|
|
|
bool hasMADIntraFwdBug() const { return HasMADIntraFwdBug; }
|
|
|
|
bool hasMSAALoadDstSelBug() const { return HasMSAALoadDstSelBug; }
|
|
|
|
bool hasPrivEnabledTrap2NopBug() const { return HasPrivEnabledTrap2NopBug; }
|
|
|
|
bool hasNSAEncoding() const { return HasNSAEncoding; }
|
|
|
|
bool hasNonNSAEncoding() const { return getGeneration() < GFX12; }
|
|
|
|
bool hasPartialNSAEncoding() const { return HasPartialNSAEncoding; }
|
|
|
|
unsigned getNSAMaxSize(bool HasSampler = false) const {
|
|
return AMDGPU::getNSAMaxSize(*this, HasSampler);
|
|
}
|
|
|
|
bool hasGFX10_AEncoding() const {
|
|
return GFX10_AEncoding;
|
|
}
|
|
|
|
bool hasGFX10_BEncoding() const {
|
|
return GFX10_BEncoding;
|
|
}
|
|
|
|
bool hasGFX10_3Insts() const {
|
|
return GFX10_3Insts;
|
|
}
|
|
|
|
bool hasMadF16() const;
|
|
|
|
bool hasMovB64() const { return GFX940Insts; }
|
|
|
|
bool hasLshlAddB64() const { return GFX940Insts; }
|
|
|
|
bool enableSIScheduler() const {
|
|
return EnableSIScheduler;
|
|
}
|
|
|
|
bool loadStoreOptEnabled() const {
|
|
return EnableLoadStoreOpt;
|
|
}
|
|
|
|
bool hasSGPRInitBug() const {
|
|
return SGPRInitBug;
|
|
}
|
|
|
|
bool hasUserSGPRInit16Bug() const {
|
|
return UserSGPRInit16Bug && isWave32();
|
|
}
|
|
|
|
bool hasNegativeScratchOffsetBug() const { return NegativeScratchOffsetBug; }
|
|
|
|
bool hasNegativeUnalignedScratchOffsetBug() const {
|
|
return NegativeUnalignedScratchOffsetBug;
|
|
}
|
|
|
|
bool hasMFMAInlineLiteralBug() const {
|
|
return HasMFMAInlineLiteralBug;
|
|
}
|
|
|
|
bool has12DWordStoreHazard() const {
|
|
return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
|
|
}
|
|
|
|
// \returns true if the subtarget supports DWORDX3 load/store instructions.
|
|
bool hasDwordx3LoadStores() const {
|
|
return CIInsts;
|
|
}
|
|
|
|
bool hasReadM0MovRelInterpHazard() const {
|
|
return getGeneration() == AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
bool hasReadM0SendMsgHazard() const {
|
|
return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
|
|
getGeneration() <= AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
bool hasReadM0LdsDmaHazard() const {
|
|
return getGeneration() == AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
bool hasReadM0LdsDirectHazard() const {
|
|
return getGeneration() == AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
bool hasVcmpxPermlaneHazard() const {
|
|
return HasVcmpxPermlaneHazard;
|
|
}
|
|
|
|
bool hasVMEMtoScalarWriteHazard() const {
|
|
return HasVMEMtoScalarWriteHazard;
|
|
}
|
|
|
|
bool hasSMEMtoVectorWriteHazard() const {
|
|
return HasSMEMtoVectorWriteHazard;
|
|
}
|
|
|
|
bool hasLDSMisalignedBug() const {
|
|
return LDSMisalignedBug && !EnableCuMode;
|
|
}
|
|
|
|
bool hasInstFwdPrefetchBug() const {
|
|
return HasInstFwdPrefetchBug;
|
|
}
|
|
|
|
bool hasVcmpxExecWARHazard() const {
|
|
return HasVcmpxExecWARHazard;
|
|
}
|
|
|
|
bool hasLdsBranchVmemWARHazard() const {
|
|
return HasLdsBranchVmemWARHazard;
|
|
}
|
|
|
|
// Shift amount of a 64 bit shift cannot be a highest allocated register
|
|
// if also at the end of the allocation block.
|
|
bool hasShift64HighRegBug() const {
|
|
return GFX90AInsts && !GFX940Insts;
|
|
}
|
|
|
|
// Has one cycle hazard on transcendental instruction feeding a
|
|
// non transcendental VALU.
|
|
bool hasTransForwardingHazard() const { return GFX940Insts; }
|
|
|
|
// Has one cycle hazard on a VALU instruction partially writing dst with
|
|
// a shift of result bits feeding another VALU instruction.
|
|
bool hasDstSelForwardingHazard() const { return GFX940Insts; }
|
|
|
|
// Cannot use op_sel with v_dot instructions.
|
|
bool hasDOTOpSelHazard() const { return GFX940Insts || GFX11Insts; }
|
|
|
|
// Does not have HW interlocs for VALU writing and then reading SGPRs.
|
|
bool hasVDecCoExecHazard() const {
|
|
return GFX940Insts;
|
|
}
|
|
|
|
bool hasNSAtoVMEMBug() const {
|
|
return HasNSAtoVMEMBug;
|
|
}
|
|
|
|
bool hasNSAClauseBug() const { return HasNSAClauseBug; }
|
|
|
|
bool hasHardClauses() const { return MaxHardClauseLength > 0; }
|
|
|
|
bool hasGFX90AInsts() const { return GFX90AInsts; }
|
|
|
|
bool hasFPAtomicToDenormModeHazard() const {
|
|
return getGeneration() == GFX10;
|
|
}
|
|
|
|
bool hasVOP3DPP() const { return getGeneration() >= GFX11; }
|
|
|
|
bool hasLdsDirect() const { return getGeneration() >= GFX11; }
|
|
|
|
bool hasLdsWaitVMSRC() const { return getGeneration() >= GFX12; }
|
|
|
|
bool hasVALUPartialForwardingHazard() const {
|
|
return getGeneration() == GFX11;
|
|
}
|
|
|
|
bool hasVALUTransUseHazard() const { return HasVALUTransUseHazard; }
|
|
|
|
bool hasCvtScaleForwardingHazard() const { return GFX950Insts; }
|
|
|
|
bool hasForceStoreSC0SC1() const { return HasForceStoreSC0SC1; }
|
|
|
|
bool requiresCodeObjectV6() const { return RequiresCOV6; }
|
|
|
|
bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; }
|
|
|
|
bool hasVALUReadSGPRHazard() const { return getGeneration() == GFX12; }
|
|
|
|
/// Return if operations acting on VGPR tuples require even alignment.
|
|
bool needsAlignedVGPRs() const { return GFX90AInsts; }
|
|
|
|
/// Return true if the target has the S_PACK_HL_B32_B16 instruction.
|
|
bool hasSPackHL() const { return GFX11Insts; }
|
|
|
|
/// Return true if the target's EXP instruction has the COMPR flag, which
|
|
/// affects the meaning of the EN (enable) bits.
|
|
bool hasCompressedExport() const { return !GFX11Insts; }
|
|
|
|
/// Return true if the target's EXP instruction supports the NULL export
|
|
/// target.
|
|
bool hasNullExportTarget() const { return !GFX11Insts; }
|
|
|
|
bool has1_5xVGPRs() const { return Has1_5xVGPRs; }
|
|
|
|
bool hasVOPDInsts() const { return HasVOPDInsts; }
|
|
|
|
bool hasFlatScratchSVSSwizzleBug() const { return getGeneration() == GFX11; }
|
|
|
|
/// Return true if the target has the S_DELAY_ALU instruction.
|
|
bool hasDelayAlu() const { return GFX11Insts; }
|
|
|
|
bool hasPackedTID() const { return HasPackedTID; }
|
|
|
|
// GFX940 is a derivation to GFX90A. hasGFX940Insts() being true implies that
|
|
// hasGFX90AInsts is also true.
|
|
bool hasGFX940Insts() const { return GFX940Insts; }
|
|
|
|
// GFX950 is a derivation to GFX940. hasGFX950Insts() implies that
|
|
// hasGFX940Insts and hasGFX90AInsts are also true.
|
|
bool hasGFX950Insts() const { return GFX950Insts; }
|
|
|
|
/// Returns true if the target supports
|
|
/// global_load_lds_dwordx3/global_load_lds_dwordx4 or
|
|
/// buffer_load_dwordx3/buffer_load_dwordx4 with the lds bit.
|
|
bool hasLDSLoadB96_B128() const {
|
|
return hasGFX950Insts();
|
|
}
|
|
|
|
bool hasSALUFloatInsts() const { return HasSALUFloatInsts; }
|
|
|
|
bool hasPseudoScalarTrans() const { return HasPseudoScalarTrans; }
|
|
|
|
bool hasRestrictedSOffset() const { return HasRestrictedSOffset; }
|
|
|
|
bool hasRequiredExportPriority() const { return HasRequiredExportPriority; }
|
|
|
|
bool hasVmemWriteVgprInOrder() const { return HasVmemWriteVgprInOrder; }
|
|
|
|
/// \returns true if the target uses LOADcnt/SAMPLEcnt/BVHcnt, DScnt/KMcnt
|
|
/// and STOREcnt rather than VMcnt, LGKMcnt and VScnt respectively.
|
|
bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; }
|
|
|
|
/// \returns true if inline constants are not supported for F16 pseudo
|
|
/// scalar transcendentals.
|
|
bool hasNoF16PseudoScalarTransInlineConstants() const {
|
|
return getGeneration() == GFX12;
|
|
}
|
|
|
|
/// \returns true if the target has instructions with xf32 format support.
|
|
bool hasXF32Insts() const { return HasXF32Insts; }
|
|
|
|
bool hasBitOp3Insts() const { return HasBitOp3Insts; }
|
|
|
|
bool hasPermlane16Swap() const { return HasPermlane16Swap; }
|
|
bool hasPermlane32Swap() const { return HasPermlane32Swap; }
|
|
bool hasAshrPkInsts() const { return HasAshrPkInsts; }
|
|
|
|
bool hasMinimum3Maximum3F32() const {
|
|
return HasMinimum3Maximum3F32;
|
|
}
|
|
|
|
bool hasMinimum3Maximum3F16() const {
|
|
return HasMinimum3Maximum3F16;
|
|
}
|
|
|
|
bool hasMinimum3Maximum3PKF16() const {
|
|
return HasMinimum3Maximum3PKF16;
|
|
}
|
|
|
|
/// \returns The maximum number of instructions that can be enclosed in an
|
|
/// S_CLAUSE on the given subtarget, or 0 for targets that do not support that
|
|
/// instruction.
|
|
unsigned maxHardClauseLength() const { return MaxHardClauseLength; }
|
|
|
|
bool hasPrngInst() const { return HasPrngInst; }
|
|
|
|
/// Return the maximum number of waves per SIMD for kernels using \p SGPRs
|
|
/// SGPRs
|
|
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
|
|
|
|
/// Return the maximum number of waves per SIMD for kernels using \p VGPRs
|
|
/// VGPRs
|
|
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
|
|
|
|
/// Subtarget's minimum/maximum occupancy, in number of waves per EU, that can
|
|
/// be achieved when the only function running on a CU is \p F, each workgroup
|
|
/// uses \p LDSSize bytes of LDS, and each wave uses \p NumSGPRs SGPRs and \p
|
|
/// NumVGPRs VGPRs. The flat workgroup sizes associated to the function are a
|
|
/// range, so this returns a range as well.
|
|
///
|
|
/// Note that occupancy can be affected by the scratch allocation as well, but
|
|
/// we do not have enough information to compute it.
|
|
std::pair<unsigned, unsigned> computeOccupancy(const Function &F,
|
|
unsigned LDSSize = 0,
|
|
unsigned NumSGPRs = 0,
|
|
unsigned NumVGPRs = 0) const;
|
|
|
|
/// \returns true if the flat_scratch register should be initialized with the
|
|
/// pointer to the wave's scratch memory rather than a size and offset.
|
|
bool flatScratchIsPointer() const {
|
|
return getGeneration() >= AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
/// \returns true if the flat_scratch register is initialized by the HW.
|
|
/// In this case it is readonly.
|
|
bool flatScratchIsArchitected() const { return HasArchitectedFlatScratch; }
|
|
|
|
/// \returns true if the architected SGPRs are enabled.
|
|
bool hasArchitectedSGPRs() const { return HasArchitectedSGPRs; }
|
|
|
|
/// \returns true if Global Data Share is supported.
|
|
bool hasGDS() const { return HasGDS; }
|
|
|
|
/// \returns true if Global Wave Sync is supported.
|
|
bool hasGWS() const { return HasGWS; }
|
|
|
|
/// \returns true if the machine has merged shaders in which s0-s7 are
|
|
/// reserved by the hardware and user SGPRs start at s8
|
|
bool hasMergedShaders() const {
|
|
return getGeneration() >= GFX9;
|
|
}
|
|
|
|
// \returns true if the target supports the pre-NGG legacy geometry path.
|
|
bool hasLegacyGeometry() const { return getGeneration() < GFX11; }
|
|
|
|
// \returns true if preloading kernel arguments is supported.
|
|
bool hasKernargPreload() const { return KernargPreload; }
|
|
|
|
// \returns true if the target has split barriers feature
|
|
bool hasSplitBarriers() const { return getGeneration() >= GFX12; }
|
|
|
|
// \returns true if FP8/BF8 VOP1 form of conversion to F32 is unreliable.
|
|
bool hasCvtFP8VOP1Bug() const { return HasCvtFP8Vop1Bug; }
|
|
|
|
// \returns true if CSUB (a.k.a. SUB_CLAMP on GFX12) atomics support a
|
|
// no-return form.
|
|
bool hasAtomicCSubNoRtnInsts() const { return HasAtomicCSubNoRtnInsts; }
|
|
|
|
// \returns true if the target has DX10_CLAMP kernel descriptor mode bit
|
|
bool hasDX10ClampMode() const { return getGeneration() < GFX12; }
|
|
|
|
// \returns true if the target has IEEE kernel descriptor mode bit
|
|
bool hasIEEEMode() const { return getGeneration() < GFX12; }
|
|
|
|
// \returns true if the target has IEEE fminimum/fmaximum instructions
|
|
bool hasIEEEMinMax() const { return getGeneration() >= GFX12; }
|
|
|
|
// \returns true if the target has IEEE fminimum3/fmaximum3 instructions
|
|
bool hasIEEEMinMax3() const { return hasIEEEMinMax(); }
|
|
|
|
// \returns true if the target has WG_RR_MODE kernel descriptor mode bit
|
|
bool hasRrWGMode() const { return getGeneration() >= GFX12; }
|
|
|
|
/// \returns true if VADDR and SADDR fields in VSCRATCH can use negative
|
|
/// values.
|
|
bool hasSignedScratchOffsets() const { return getGeneration() >= GFX12; }
|
|
|
|
// \returns true if S_GETPC_B64 zero-extends the result from 48 bits instead
|
|
// of sign-extending.
|
|
bool hasGetPCZeroExtension() const { return GFX12Insts; }
|
|
|
|
/// \returns SGPR allocation granularity supported by the subtarget.
|
|
unsigned getSGPRAllocGranule() const {
|
|
return AMDGPU::IsaInfo::getSGPRAllocGranule(this);
|
|
}
|
|
|
|
/// \returns SGPR encoding granularity supported by the subtarget.
|
|
unsigned getSGPREncodingGranule() const {
|
|
return AMDGPU::IsaInfo::getSGPREncodingGranule(this);
|
|
}
|
|
|
|
/// \returns Total number of SGPRs supported by the subtarget.
|
|
unsigned getTotalNumSGPRs() const {
|
|
return AMDGPU::IsaInfo::getTotalNumSGPRs(this);
|
|
}
|
|
|
|
/// \returns Addressable number of SGPRs supported by the subtarget.
|
|
unsigned getAddressableNumSGPRs() const {
|
|
return AMDGPU::IsaInfo::getAddressableNumSGPRs(this);
|
|
}
|
|
|
|
/// \returns Minimum number of SGPRs that meets the given number of waves per
|
|
/// execution unit requirement supported by the subtarget.
|
|
unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
|
|
return AMDGPU::IsaInfo::getMinNumSGPRs(this, WavesPerEU);
|
|
}
|
|
|
|
/// \returns Maximum number of SGPRs that meets the given number of waves per
|
|
/// execution unit requirement supported by the subtarget.
|
|
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
|
|
return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable);
|
|
}
|
|
|
|
/// \returns Reserved number of SGPRs. This is common
|
|
/// utility function called by MachineFunction and
|
|
/// Function variants of getReservedNumSGPRs.
|
|
unsigned getBaseReservedNumSGPRs(const bool HasFlatScratch) const;
|
|
/// \returns Reserved number of SGPRs for given machine function \p MF.
|
|
unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
|
|
|
|
/// \returns Reserved number of SGPRs for given function \p F.
|
|
unsigned getReservedNumSGPRs(const Function &F) const;
|
|
|
|
/// \returns max num SGPRs. This is the common utility
|
|
/// function called by MachineFunction and Function
|
|
/// variants of getMaxNumSGPRs.
|
|
unsigned getBaseMaxNumSGPRs(const Function &F,
|
|
std::pair<unsigned, unsigned> WavesPerEU,
|
|
unsigned PreloadedSGPRs,
|
|
unsigned ReservedNumSGPRs) const;
|
|
|
|
/// \returns Maximum number of SGPRs that meets number of waves per execution
|
|
/// unit requirement for function \p MF, or number of SGPRs explicitly
|
|
/// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
|
|
///
|
|
/// \returns Value that meets number of waves per execution unit requirement
|
|
/// if explicitly requested value cannot be converted to integer, violates
|
|
/// subtarget's specifications, or does not meet number of waves per execution
|
|
/// unit requirement.
|
|
unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
|
|
|
|
/// \returns Maximum number of SGPRs that meets number of waves per execution
|
|
/// unit requirement for function \p F, or number of SGPRs explicitly
|
|
/// requested using "amdgpu-num-sgpr" attribute attached to function \p F.
|
|
///
|
|
/// \returns Value that meets number of waves per execution unit requirement
|
|
/// if explicitly requested value cannot be converted to integer, violates
|
|
/// subtarget's specifications, or does not meet number of waves per execution
|
|
/// unit requirement.
|
|
unsigned getMaxNumSGPRs(const Function &F) const;
|
|
|
|
/// \returns VGPR allocation granularity supported by the subtarget.
|
|
unsigned getVGPRAllocGranule() const {
|
|
return AMDGPU::IsaInfo::getVGPRAllocGranule(this);
|
|
}
|
|
|
|
/// \returns VGPR encoding granularity supported by the subtarget.
|
|
unsigned getVGPREncodingGranule() const {
|
|
return AMDGPU::IsaInfo::getVGPREncodingGranule(this);
|
|
}
|
|
|
|
/// \returns Total number of VGPRs supported by the subtarget.
|
|
unsigned getTotalNumVGPRs() const {
|
|
return AMDGPU::IsaInfo::getTotalNumVGPRs(this);
|
|
}
|
|
|
|
/// \returns Addressable number of architectural VGPRs supported by the
|
|
/// subtarget.
|
|
unsigned getAddressableNumArchVGPRs() const {
|
|
return AMDGPU::IsaInfo::getAddressableNumArchVGPRs(this);
|
|
}
|
|
|
|
/// \returns Addressable number of VGPRs supported by the subtarget.
|
|
unsigned getAddressableNumVGPRs() const {
|
|
return AMDGPU::IsaInfo::getAddressableNumVGPRs(this);
|
|
}
|
|
|
|
/// \returns the minimum number of VGPRs that will prevent achieving more than
|
|
/// the specified number of waves \p WavesPerEU.
|
|
unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
|
|
return AMDGPU::IsaInfo::getMinNumVGPRs(this, WavesPerEU);
|
|
}
|
|
|
|
/// \returns the maximum number of VGPRs that can be used and still achieved
|
|
/// at least the specified number of waves \p WavesPerEU.
|
|
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
|
|
return AMDGPU::IsaInfo::getMaxNumVGPRs(this, WavesPerEU);
|
|
}
|
|
|
|
/// \returns max num VGPRs. This is the common utility function
|
|
/// called by MachineFunction and Function variants of getMaxNumVGPRs.
|
|
unsigned getBaseMaxNumVGPRs(const Function &F,
|
|
std::pair<unsigned, unsigned> WavesPerEU) const;
|
|
/// \returns Maximum number of VGPRs that meets number of waves per execution
|
|
/// unit requirement for function \p F, or number of VGPRs explicitly
|
|
/// requested using "amdgpu-num-vgpr" attribute attached to function \p F.
|
|
///
|
|
/// \returns Value that meets number of waves per execution unit requirement
|
|
/// if explicitly requested value cannot be converted to integer, violates
|
|
/// subtarget's specifications, or does not meet number of waves per execution
|
|
/// unit requirement.
|
|
unsigned getMaxNumVGPRs(const Function &F) const;
|
|
|
|
unsigned getMaxNumAGPRs(const Function &F) const {
|
|
return getMaxNumVGPRs(F);
|
|
}
|
|
|
|
/// \returns Maximum number of VGPRs that meets number of waves per execution
|
|
/// unit requirement for function \p MF, or number of VGPRs explicitly
|
|
/// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
|
|
///
|
|
/// \returns Value that meets number of waves per execution unit requirement
|
|
/// if explicitly requested value cannot be converted to integer, violates
|
|
/// subtarget's specifications, or does not meet number of waves per execution
|
|
/// unit requirement.
|
|
unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
|
|
|
|
bool isWave32() const {
|
|
return getWavefrontSize() == 32;
|
|
}
|
|
|
|
bool isWave64() const {
|
|
return getWavefrontSize() == 64;
|
|
}
|
|
|
|
/// Returns if the wavesize of this subtarget is known reliable. This is false
|
|
/// only for the a default target-cpu that does not have an explicit
|
|
/// +wavefrontsize target feature.
|
|
bool isWaveSizeKnown() const {
|
|
return hasFeature(AMDGPU::FeatureWavefrontSize32) ||
|
|
hasFeature(AMDGPU::FeatureWavefrontSize64);
|
|
}
|
|
|
|
const TargetRegisterClass *getBoolRC() const {
|
|
return getRegisterInfo()->getBoolRC();
|
|
}
|
|
|
|
/// \returns Maximum number of work groups per compute unit supported by the
|
|
/// subtarget and limited by given \p FlatWorkGroupSize.
|
|
unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
|
|
return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
|
|
}
|
|
|
|
/// \returns Minimum flat work group size supported by the subtarget.
|
|
unsigned getMinFlatWorkGroupSize() const override {
|
|
return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
|
|
}
|
|
|
|
/// \returns Maximum flat work group size supported by the subtarget.
|
|
unsigned getMaxFlatWorkGroupSize() const override {
|
|
return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
|
|
}
|
|
|
|
/// \returns Number of waves per execution unit required to support the given
|
|
/// \p FlatWorkGroupSize.
|
|
unsigned
|
|
getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
|
|
return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize);
|
|
}
|
|
|
|
/// \returns Minimum number of waves per execution unit supported by the
|
|
/// subtarget.
|
|
unsigned getMinWavesPerEU() const override {
|
|
return AMDGPU::IsaInfo::getMinWavesPerEU(this);
|
|
}
|
|
|
|
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
|
|
SDep &Dep,
|
|
const TargetSchedModel *SchedModel) const override;
|
|
|
|
// \returns true if it's beneficial on this subtarget for the scheduler to
|
|
// cluster stores as well as loads.
|
|
bool shouldClusterStores() const { return getGeneration() >= GFX11; }
|
|
|
|
// \returns the number of address arguments from which to enable MIMG NSA
|
|
// on supported architectures.
|
|
unsigned getNSAThreshold(const MachineFunction &MF) const;
|
|
|
|
// \returns true if the subtarget has a hazard requiring an "s_nop 0"
|
|
// instruction before "s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)".
|
|
bool requiresNopBeforeDeallocVGPRs() const {
|
|
// Currently all targets that support the dealloc VGPRs message also require
|
|
// the nop.
|
|
return true;
|
|
}
|
|
|
|
bool requiresDisjointEarlyClobberAndUndef() const override {
|
|
// AMDGPU doesn't care if early-clobber and undef operands are allocated
|
|
// to the same register.
|
|
return false;
|
|
}
|
|
};
|
|
|
|
class GCNUserSGPRUsageInfo {
|
|
public:
|
|
bool hasImplicitBufferPtr() const { return ImplicitBufferPtr; }
|
|
|
|
bool hasPrivateSegmentBuffer() const { return PrivateSegmentBuffer; }
|
|
|
|
bool hasDispatchPtr() const { return DispatchPtr; }
|
|
|
|
bool hasQueuePtr() const { return QueuePtr; }
|
|
|
|
bool hasKernargSegmentPtr() const { return KernargSegmentPtr; }
|
|
|
|
bool hasDispatchID() const { return DispatchID; }
|
|
|
|
bool hasFlatScratchInit() const { return FlatScratchInit; }
|
|
|
|
bool hasPrivateSegmentSize() const { return PrivateSegmentSize; }
|
|
|
|
unsigned getNumKernargPreloadSGPRs() const { return NumKernargPreloadSGPRs; }
|
|
|
|
unsigned getNumUsedUserSGPRs() const { return NumUsedUserSGPRs; }
|
|
|
|
unsigned getNumFreeUserSGPRs();
|
|
|
|
void allocKernargPreloadSGPRs(unsigned NumSGPRs);
|
|
|
|
enum UserSGPRID : unsigned {
|
|
ImplicitBufferPtrID = 0,
|
|
PrivateSegmentBufferID = 1,
|
|
DispatchPtrID = 2,
|
|
QueuePtrID = 3,
|
|
KernargSegmentPtrID = 4,
|
|
DispatchIdID = 5,
|
|
FlatScratchInitID = 6,
|
|
PrivateSegmentSizeID = 7
|
|
};
|
|
|
|
// Returns the size in number of SGPRs for preload user SGPR field.
|
|
static unsigned getNumUserSGPRForField(UserSGPRID ID) {
|
|
switch (ID) {
|
|
case ImplicitBufferPtrID:
|
|
return 2;
|
|
case PrivateSegmentBufferID:
|
|
return 4;
|
|
case DispatchPtrID:
|
|
return 2;
|
|
case QueuePtrID:
|
|
return 2;
|
|
case KernargSegmentPtrID:
|
|
return 2;
|
|
case DispatchIdID:
|
|
return 2;
|
|
case FlatScratchInitID:
|
|
return 2;
|
|
case PrivateSegmentSizeID:
|
|
return 1;
|
|
}
|
|
llvm_unreachable("Unknown UserSGPRID.");
|
|
}
|
|
|
|
GCNUserSGPRUsageInfo(const Function &F, const GCNSubtarget &ST);
|
|
|
|
private:
|
|
const GCNSubtarget &ST;
|
|
|
|
// Private memory buffer
|
|
// Compute directly in sgpr[0:1]
|
|
// Other shaders indirect 64-bits at sgpr[0:1]
|
|
bool ImplicitBufferPtr = false;
|
|
|
|
bool PrivateSegmentBuffer = false;
|
|
|
|
bool DispatchPtr = false;
|
|
|
|
bool QueuePtr = false;
|
|
|
|
bool KernargSegmentPtr = false;
|
|
|
|
bool DispatchID = false;
|
|
|
|
bool FlatScratchInit = false;
|
|
|
|
bool PrivateSegmentSize = false;
|
|
|
|
unsigned NumKernargPreloadSGPRs = 0;
|
|
|
|
unsigned NumUsedUserSGPRs = 0;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
|