clang-p2996

AsmParser

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

Disassembler

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

GISel

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587 )

2025-01-07 18:53:10 -08:00

MCA

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MCTargetDesc

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

TargetInfo

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CMakeLists.txt

[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866 )

2025-01-07 09:51:34 -08:00

RISCV.h

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCV.td

[RISCV] Add P550 scheduler model. (#124639 )

2025-01-27 22:40:05 -08:00

RISCVAsmPrinter.cpp

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RISCVCallingConv.cpp

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RISCVCallingConv.h

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RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

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RISCVCombine.td

[GISel] Combine (neg (min/max x, (neg x))) into (max/min x, (neg x)) (#120998 )

2025-01-02 16:29:34 -08:00

RISCVConstantPoolValue.cpp

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RISCVConstantPoolValue.h

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RISCVDeadRegisterDefinitions.cpp

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RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Support multiple memory operands in expandRV32ZdinxStore.

2025-01-27 22:10:51 -08:00

RISCVFeatures.td

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVFrameLowering.cpp

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623 )

2025-01-28 21:03:12 +05:30

RISCVFrameLowering.h

[RISCV] Stack clash protection for dynamic alloca (#122508 )

2025-01-16 11:58:42 -08:00

RISCVGatherScatterLowering.cpp

[RISCV] Allow non-loop invariant steps in RISCVGatherScatterLowering (#122244 )

2025-01-17 08:58:56 +08:00

RISCVGISel.td

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RISCVIndirectBranchTracking.cpp

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RISCVInsertReadWriteCSR.cpp

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RISCVInsertVSETVLI.cpp

[RISCV] Use llvm::reverse instead of make_range(rbegin, rend). NFC

2025-01-28 16:08:29 +08:00

RISCVInsertWriteVXRM.cpp

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RISCVInstrFormats.td

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RISCVInstrFormatsC.td

[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC

2025-01-10 14:28:54 -08:00

RISCVInstrFormatsV.td

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RISCVInstrGISel.td

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RISCVInstrInfo.cpp

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623 )

2025-01-28 21:03:12 +05:30

RISCVInstrInfo.h

[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC) (#120622 )

2025-01-22 13:36:39 +05:30

RISCVInstrInfo.td

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVInstrInfoA.td

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RISCVInstrInfoC.td

[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC

2025-01-10 14:28:54 -08:00

RISCVInstrInfoD.td

[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379 )

2025-01-07 07:50:50 -08:00

RISCVInstrInfoF.td

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RISCVInstrInfoM.td

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RISCVInstrInfoSFB.td

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RISCVInstrInfoV.td

[RISCV][MC] Create an AsmOperand for carry-in vmask (#124317 )

2025-01-24 13:02:33 -08:00

RISCVInstrInfoVPseudos.td

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

RISCVInstrInfoVSDPatterns.td

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RISCVInstrInfoVVLPatterns.td

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RISCVInstrInfoXCV.td

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RISCVInstrInfoXMips.td

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVInstrInfoXqci.td

[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237 )

2025-01-27 20:40:45 -08:00

RISCVInstrInfoXSf.td

[RISCV] Add @earlyclobber to SiFive custom matrix multiply instruction. (#124060 )

2025-01-23 08:26:39 -08:00

RISCVInstrInfoXTHead.td

[RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC

2024-12-29 12:44:33 -08:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoXwch.td

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RISCVInstrInfoZa.td

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RISCVInstrInfoZalasr.td

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RISCVInstrInfoZb.td

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RISCVInstrInfoZc.td

[RISCV] Simplify some RISCVInstrInfoC classes by removing arguments that never change. NFC

2025-01-09 16:21:55 -08:00

RISCVInstrInfoZcmop.td

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RISCVInstrInfoZfa.td

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RISCVInstrInfoZfbfmin.td

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RISCVInstrInfoZfh.td

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RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

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RISCVInstrInfoZicond.td

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RISCVInstrInfoZimop.td

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RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

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RISCVInstrInfoZvk.td

[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345 )

2025-01-22 07:42:27 +01:00

RISCVISelDAGToDAG.cpp

[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345 )

2025-01-22 07:42:27 +01:00

RISCVISelDAGToDAG.h

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RISCVISelLowering.cpp

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVISelLowering.h

[IA] Generalize the support for power-of-two (de)interleave intrinsics (#123863 )

2025-01-23 15:27:51 -08:00

RISCVLandingPadSetup.cpp

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RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

[RISCV] Stack clash protection for dynamic alloca (#122508 )

2025-01-16 11:58:42 -08:00

RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

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RISCVMergeBaseOffset.cpp

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RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

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RISCVPfmCounters.td

[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866 )

2025-01-07 09:51:34 -08:00

RISCVPostRAExpandPseudoInsts.cpp

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RISCVProcessors.td

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVProfiles.td

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RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV] Add register allocation hints for lui/auipc+addi fusion. (#123860 )

2025-01-27 11:16:22 -08:00

RISCVRegisterInfo.h

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RISCVRegisterInfo.td

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RISCVSchedMIPSP8700.td

[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865 )

2025-01-22 10:37:01 -08:00

RISCVSchedRocket.td

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RISCVSchedSiFive7.td

[RISCV][SIFIVE] Fix latencies for vector integer arithmetic long latency (#124855 )

2025-01-29 09:42:51 -05:00

RISCVSchedSiFiveP400.td

[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model (#122007 )

2025-01-07 15:01:05 -08:00

RISCVSchedSiFiveP500.td

[RISCV] Add P550 scheduler model. (#124639 )

2025-01-27 22:40:05 -08:00

RISCVSchedSiFiveP600.td

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RISCVSchedSyntacoreSCR1.td

[RISCV] Remove some unnecessary UnsupportedSched* that are implied by others. NFC

2025-01-21 18:00:52 -08:00

RISCVSchedSyntacoreSCR7.td

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RISCVSchedSyntacoreSCR345.td

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RISCVSchedTTAscalonD8.td

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RISCVSchedule.td

[RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh

2024-12-31 17:22:08 +08:00

RISCVScheduleV.td

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RISCVScheduleXSf.td

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RISCVScheduleZb.td

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RISCVScheduleZvk.td

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RISCVSchedXiangShanNanHu.td

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RISCVSelectionDAGInfo.cpp

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RISCVSelectionDAGInfo.h

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RISCVSubtarget.cpp

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVSubtarget.h

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVSystemOperands.td

[RISCV] Add Enum for CSR encodings. (#121674 )

2025-01-06 10:11:29 -08:00

RISCVTargetMachine.cpp

[RISCV] Add MIPS extensions (#121394 )

2025-01-28 08:04:09 +01:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

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RISCVTargetObjectFile.h

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RISCVTargetTransformInfo.cpp

[RISCV][TTI]Use processShuffleMasks for cost estimations/actual per-register shuffles

2025-01-29 07:18:55 -05:00

RISCVTargetTransformInfo.h

[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533 )

2024-12-31 10:56:28 +08:00

RISCVVectorMaskDAGMutation.cpp

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RISCVVectorPeephole.cpp

[RISCV] Fix masked->unmasked peephole handling masked pseudos with no passthru (#122253 )

2025-01-09 19:54:37 +08:00

RISCVVLOptimizer.cpp

[RISCV][VLOPT] Compute demanded VLs up front (#124530 )

2025-01-29 12:39:38 +08:00

RISCVZacasABIFix.cpp

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