9843843c88
This fixes DAG divergence mishandling inline asm. This was considering the glue nodes for divergence, when the divergence should only come from the individual CopyFromRegs that are glued. As a result, having any VGPR CopyFromRegs would taint any uniform SGPR copies as divergent, resulting in SGPR copies to VGPR virtual registers later.
48 lines
1.8 KiB
LLVM
48 lines
1.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}private_load_maybe_divergent:
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; GCN: buffer_load_dword
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; GCN-NOT: s_load_dword s
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; GCN: flat_load_dword
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; GCN-NOT: s_load_dword s
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define amdgpu_kernel void @private_load_maybe_divergent(ptr addrspace(4) %k, ptr %flat) {
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%load = load volatile i32, ptr addrspace(5) undef, align 4
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%gep = getelementptr inbounds i32, ptr addrspace(4) %k, i32 %load
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%maybe.not.uniform.load = load i32, ptr addrspace(4) %gep, align 4
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store i32 %maybe.not.uniform.load, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}flat_load_maybe_divergent:
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; GCN: s_load_dwordx4
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; GCN-NOT: s_load
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; GCN: flat_load_dword
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; GCN-NOT: s_load
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; GCN: flat_load_dword
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; GCN-NOT: s_load
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; GCN: flat_store_dword
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define amdgpu_kernel void @flat_load_maybe_divergent(ptr addrspace(4) %k, ptr %flat) {
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%load = load i32, ptr %flat, align 4
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%gep = getelementptr inbounds i32, ptr addrspace(4) %k, i32 %load
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%maybe.not.uniform.load = load i32, ptr addrspace(4) %gep, align 4
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store i32 %maybe.not.uniform.load, ptr addrspace(1) undef
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ret void
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}
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; This decomposes into a sequence of divergent sub carries. The first
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; subs in the sequence are divergent from the value inputs, but the
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; last values are divergent due to the carry in glue (such that
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; divergence needs to propagate through glue if there are any non-void
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; outputs)
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; GCN-LABEL: {{^}}wide_carry_divergence_error:
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; GCN: v_sub_u32_e32
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; GCN: v_subb_u32_e32
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; GCN: v_subbrev_u32_e32
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; GCN: v_subbrev_u32_e32
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define <2 x i128> @wide_carry_divergence_error(i128 %arg) {
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%i = call i128 @llvm.ctlz.i128(i128 %arg, i1 false)
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%i1 = sub i128 0, %i
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%i2 = insertelement <2 x i128> zeroinitializer, i128 %i1, i64 0
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ret <2 x i128> %i2
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}
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