9cf68679c4
This test case was failing to compile with a "ran out of registers during register allocation" error at -O0. This was because CMP_SWAP_64 has 3 operands which must be an even-odd register pair, and two other GPR operands. All of the def operands are also early-clobber, so registers can't be shared between uses and defs. Because the function has an over-aligned alloca it needs frame and base pointers, so r6 and r11 are both reserved. That leaves r0/r1, r2/r3, r4/r5 and r8/r9 as the only valid register pairs, and if the two individual GPR operands happen to get allocated to registers in different pairs then only 2 pairs will be available for the three GPRPair operands. To fix this, I've merged the two GPR operands into a single GPRPair operand. This means that the instruction now has 4 GPRPair operands, which can always be allocated without relying on luck. This does constrain register allocation a bit more, but this pseudo instruction is only used at -O0, so I don't think that's a problem.
63 lines
2.8 KiB
YAML
63 lines
2.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
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# RUN: llc -o - %s -mtriple=armv7eb-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
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---
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name: func
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0_r1, $r4_r5, $r3, $lr
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; CHECK-LABEL: name: func
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $r0_r1, $r4_r5, $r3, $lr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: .1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $r4_r5, $r2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r0_r1 = LDREXD $r2, 14 /* CC::al */, $noreg
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; CHECK-NEXT: CMPrr killed $r0, $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: CMPrr killed $r1, $r5, 0 /* CC::eq */, killed $cpsr, implicit-def $cpsr
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; CHECK-NEXT: Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: .2:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: liveins: $r4_r5, $r2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: early-clobber $r3 = STREXD $r4_r5, $r2, 14 /* CC::al */, $noreg
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; CHECK-NEXT: CMPri killed $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: .3:
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dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2_r3 = CMP_SWAP_64 killed renamable $r2_r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic (s64))
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...
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---
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name: func2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r1, $r2, $r3, $r12, $lr
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; CHECK-LABEL: name: func2
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $r1, $r2, $r3, $r12, $lr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: .1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $lr, $r3, $r12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r1 = LDREX $r3, 14 /* CC::al */, $noreg
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; CHECK-NEXT: CMPrr killed $r1, $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: .2:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: liveins: $lr, $r3, $r12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: early-clobber $r2 = STREX $lr, $r3, 14 /* CC::al */, $noreg
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; CHECK-NEXT: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: .3:
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dead early-clobber renamable $r1, dead early-clobber renamable $r2 = CMP_SWAP_32 killed renamable $r3, killed renamable $r12, killed renamable $lr
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...
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