c5037db4ac
Similar to 806761a762
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
bpf*-apple-darwin as ELF instead of rejecting it outrightly.
113 lines
2.4 KiB
LLVM
113 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=bpfel -mcpu=v1 < %s | FileCheck --check-prefix=CHECK-V1 %s
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; RUN: llc -mtriple=bpfel -mcpu=v2 < %s | FileCheck --check-prefix=CHECK-V2 %s
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define i16 @sccweqand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp eq i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK-LABEL: sccweqand:
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; CHECK-V1: if r1 == 0
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; CHECK-V2: if r1 == 0
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define i16 @sccwneand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK-LABEL: sccwneand:
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; CHECK-V1: if r1 != 0
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; CHECK-V2: if r1 != 0
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define i16 @sccwne(i16 %a, i16 %b) nounwind {
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%t1 = icmp ne i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwne:
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; CHECK-V1: if r1 != r2
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; CHECK-V2: if r1 != r2
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define i16 @sccweq(i16 %a, i16 %b) nounwind {
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%t1 = icmp eq i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccweq:
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; CHECK-V1: if r1 == r2
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; CHECK-V2: if r1 == r2
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define i16 @sccwugt(i16 %a, i16 %b) nounwind {
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%t1 = icmp ugt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwugt:
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; CHECK-V1: if r1 > r2
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; CHECK-V2: if r1 > r2
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define i16 @sccwuge(i16 %a, i16 %b) nounwind {
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%t1 = icmp uge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwuge:
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; CHECK-V1: if r1 >= r2
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; CHECK-V2: if r1 >= r2
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define i16 @sccwult(i16 %a, i16 %b) nounwind {
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%t1 = icmp ult i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwult:
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; CHECK-V1: if r2 > r1
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; CHECK-V2: if r1 < r2
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define i16 @sccwule(i16 %a, i16 %b) nounwind {
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%t1 = icmp ule i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwule:
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; CHECK-V1: if r2 >= r1
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; CHECK-V2: if r1 <= r2
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define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
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%t1 = icmp sgt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwsgt:
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; CHECK-V1: if r1 s> r2
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; CHECK-V2: if r1 s> r2
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define i16 @sccwsge(i16 %a, i16 %b) nounwind {
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%t1 = icmp sge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwsge:
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; CHECK-V1: if r1 s>= r2
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; CHECK-V2: if r1 s>= r2
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define i16 @sccwslt(i16 %a, i16 %b) nounwind {
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%t1 = icmp slt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwslt:
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; CHECK-V1: if r2 s> r1
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; CHECK-V2: if r1 s< r2
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define i16 @sccwsle(i16 %a, i16 %b) nounwind {
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%t1 = icmp sle i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwsle:
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; CHECK-V1: if r2 s>= r1
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; CHECK-V2: if r1 s<= r2
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