c4c9d4f306
Add support for the moveq instruction, which is both faster and smaller (1/2 to 1/3 the size) than a move with immediate to register. This change introduces the instruction, along with a set of pseudoinstructions to handle immediate moves to a register that is lowered post-RA. Pseudos are used as moveq can only write to the full register, which makes matching i8 and i16 immediate loads difficult in tablegen. Furthermore, selecting moveq before RA constrains that immediate to be moved into a data register, which may not be optimal. The bulk of this change are fixes to existing tests, which cover the new functionality sufficiently.
321 lines
8.7 KiB
LLVM
321 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k -verify-machineinstrs | FileCheck %s
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define i32 @test1(ptr %y) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: cmpi.l #0, (%a0)
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; CHECK-NEXT: beq .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %cond_false
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB0_2: ; %cond_true
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; CHECK-NEXT: moveq #1, %d0
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; CHECK-NEXT: rts
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%tmp = load i32, ptr %y ; <i32> [#uses=1]
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%tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; <i1> [#uses=1]
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br i1 %tmp.upgrd.1, label %cond_true, label %cond_false
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cond_false: ; preds = %0
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ret i32 0
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cond_true: ; preds = %0
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ret i32 1
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}
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define i32 @test2(ptr %y) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.l (%a0), %d0
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; CHECK-NEXT: and.l #536870911, %d0
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; CHECK-NEXT: cmpi.l #0, %d0
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; CHECK-NEXT: beq .LBB1_2
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; CHECK-NEXT: ; %bb.1: ; %cond_false
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB1_2: ; %cond_true
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; CHECK-NEXT: moveq #1, %d0
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; CHECK-NEXT: rts
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%tmp = load i32, ptr %y ; <i32> [#uses=1]
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%tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1]
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%tmp1.upgrd.2 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false
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cond_false: ; preds = %0
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ret i32 0
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cond_true: ; preds = %0
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ret i32 1
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}
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define i8 @test2b(ptr %y) nounwind {
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; CHECK-LABEL: test2b:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.b (%a0), %d0
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; CHECK-NEXT: and.b #31, %d0
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; CHECK-NEXT: cmpi.b #0, %d0
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; CHECK-NEXT: beq .LBB2_2
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; CHECK-NEXT: ; %bb.1: ; %cond_false
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB2_2: ; %cond_true
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; CHECK-NEXT: moveq #1, %d0
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; CHECK-NEXT: rts
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%tmp = load i8, ptr %y ; <i8> [#uses=1]
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%tmp1 = shl i8 %tmp, 3 ; <i8> [#uses=1]
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%tmp1.upgrd.2 = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false
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cond_false: ; preds = %0
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ret i8 0
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cond_true: ; preds = %0
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ret i8 1
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}
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define i64 @test3(i64 %x) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (8,%sp), %d0
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; CHECK-NEXT: or.l (4,%sp), %d0
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; CHECK-NEXT: seq %d0
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; CHECK-NEXT: move.l %d0, %d1
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; CHECK-NEXT: and.l #255, %d1
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: rts
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%t = icmp eq i64 %x, 0
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%r = zext i1 %t to i64
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ret i64 %r
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}
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define i64 @test4(i64 %x) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.l (8,%sp), %d1
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: move.l (12,%sp), %d2
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; CHECK-NEXT: sub.l #1, %d2
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; CHECK-NEXT: subx.l %d0, %d1
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; CHECK-NEXT: slt %d1
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; CHECK-NEXT: and.l #255, %d1
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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%t = icmp slt i64 %x, 1
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%r = zext i1 %t to i64
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ret i64 %r
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}
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define i32 @test6() nounwind align 2 {
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; CHECK-LABEL: test6:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: suba.l #20, %sp
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; CHECK-NEXT: move.l (12,%sp), %d0
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; CHECK-NEXT: or.l (8,%sp), %d0
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; CHECK-NEXT: beq .LBB5_1
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; CHECK-NEXT: ; %bb.2: ; %F
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB5_1: ; %T
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; CHECK-NEXT: moveq #1, %d0
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; CHECK-NEXT: adda.l #20, %sp
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; CHECK-NEXT: rts
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%A = alloca {i64, i64}, align 8
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%B = getelementptr inbounds {i64, i64}, ptr %A, i64 0, i32 1
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%C = load i64, ptr %B
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%D = icmp eq i64 %C, 0
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br i1 %D, label %T, label %F
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T:
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ret i32 1
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F:
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ret i32 0
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}
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define i32 @test7(i64 %res) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: cmpi.l #0, (4,%sp)
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; CHECK-NEXT: seq %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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entry:
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%lnot = icmp ult i64 %res, 4294967296
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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}
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define i32 @test8(i64 %res) nounwind {
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; CHECK-LABEL: test8:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: sub.l #3, %d0
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; CHECK-NEXT: scs %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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entry:
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%lnot = icmp ult i64 %res, 12884901888
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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}
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define i32 @test11(i64 %l) nounwind {
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; CHECK-LABEL: test11:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: and.l #-32768, %d0
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; CHECK-NEXT: sub.l #32768, %d0
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; CHECK-NEXT: seq %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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entry:
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%shr.mask = and i64 %l, -140737488355328
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%cmp = icmp eq i64 %shr.mask, 140737488355328
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
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; CHECK-LABEL: test13:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.b (7,%sp), %d0
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; CHECK-NEXT: and.b #8, %d0
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; CHECK-NEXT: cmpi.b #0, %d0
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; CHECK-NEXT: bne .LBB9_1
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; CHECK-NEXT: ; %bb.2:
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; CHECK-NEXT: lea (8,%sp), %a0
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; CHECK-NEXT: move.l (%a0), %d0
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB9_1:
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; CHECK-NEXT: lea (12,%sp), %a0
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; CHECK-NEXT: move.l (%a0), %d0
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; CHECK-NEXT: rts
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%and = and i32 %mask, 8
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%tobool = icmp ne i32 %and, 0
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%cond = select i1 %tobool, i32 %intra, i32 %base
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ret i32 %cond
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}
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define i32 @test14(i32 %mask, i32 %base, i32 %intra) #0 {
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; CHECK-LABEL: test14:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsr.l #7, %d0
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; CHECK-NEXT: cmpi.l #0, %d0
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; CHECK-NEXT: bpl .LBB10_1
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; CHECK-NEXT: ; %bb.2:
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; CHECK-NEXT: lea (8,%sp), %a0
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; CHECK-NEXT: move.l (%a0), %d0
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB10_1:
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; CHECK-NEXT: lea (12,%sp), %a0
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; CHECK-NEXT: move.l (%a0), %d0
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; CHECK-NEXT: rts
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%s = lshr i32 %mask, 7
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%tobool = icmp sgt i32 %s, -1
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%cond = select i1 %tobool, i32 %intra, i32 %base
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ret i32 %cond
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}
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define zeroext i1 @test15(i32 %bf.load, i32 %n) {
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; CHECK-LABEL: test15:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: moveq #16, %d0
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; CHECK-NEXT: move.l (4,%sp), %d1
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; CHECK-NEXT: lsr.l %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: sub.l (8,%sp), %d0
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; CHECK-NEXT: scc %d0
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; CHECK-NEXT: cmpi.l #0, %d1
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; CHECK-NEXT: seq %d1
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; CHECK-NEXT: or.b %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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%bf.lshr = lshr i32 %bf.load, 16
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%cmp2 = icmp eq i32 %bf.lshr, 0
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%cmp5 = icmp uge i32 %bf.lshr, %n
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%.cmp5 = or i1 %cmp2, %cmp5
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ret i1 %.cmp5
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}
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define i8 @test16(i16 signext %L) {
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; CHECK-LABEL: test16:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: moveq #15, %d1
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; CHECK-NEXT: move.w (6,%sp), %d0
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; CHECK-NEXT: lsr.w %d1, %d0
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; CHECK-NEXT: eori.b #1, %d0
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; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $wd0
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; CHECK-NEXT: rts
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%lshr = lshr i16 %L, 15
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%trunc = trunc i16 %lshr to i8
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%not = xor i8 %trunc, 1
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ret i8 %not
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}
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define i8 @test18(i64 %L) {
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; CHECK-LABEL: test18:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: moveq #31, %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsr.l %d1, %d0
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; CHECK-NEXT: eori.b #1, %d0
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; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
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; CHECK-NEXT: rts
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%lshr = lshr i64 %L, 63
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%trunc = trunc i64 %lshr to i8
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%not = xor i8 %trunc, 1
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ret i8 %not
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}
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@d = global i8 0, align 1
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define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
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; CHECK-LABEL: test20:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -8
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.l #16777215, %d0
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; CHECK-NEXT: and.l (8,%sp), %d0
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; CHECK-NEXT: sne %d1
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; CHECK-NEXT: and.l #255, %d1
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; CHECK-NEXT: move.l (16,%sp), %a0
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; CHECK-NEXT: move.b (15,%sp), %d2
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; CHECK-NEXT: and.l #255, %d2
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; CHECK-NEXT: add.l %d1, %d2
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; CHECK-NEXT: sne (%a0)
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; CHECK-NEXT: cmpi.l #0, %d0
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; CHECK-NEXT: lea (d,%pc), %a0
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; CHECK-NEXT: sne (%a0)
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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%bf.shl = shl i32 %bf.load, 8
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%bf.ashr = ashr exact i32 %bf.shl, 8
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%tobool4 = icmp ne i32 %bf.ashr, 0
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%conv = zext i1 %tobool4 to i32
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%conv6 = zext i8 %x1 to i32
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%add = add nuw nsw i32 %conv, %conv6
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%tobool7 = icmp ne i32 %add, 0
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%frombool = zext i1 %tobool7 to i8
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store i8 %frombool, ptr %b_addr, align 1
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%tobool14 = icmp ne i32 %bf.shl, 0
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%frombool15 = zext i1 %tobool14 to i8
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store i8 %frombool15, ptr @d, align 1
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ret void
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}
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