cba70550cc
The "topological" sorting was behaving incorrectly in some cases: the exit of a loop could have a lower rank than a node in the loop. This causes issues when structurizing some patterns, and also codegen issues as we could generate BBs in the incorrect order in regard to the SPIR-V spec. Fixing this ordering alone broke other parts of the structurizer, which by luck worked. Had to fix those. Added more test cases, especially to test basic patterns. I also needed to tweak/disable some tests for 2 reasons: - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores are optimized away. Some tests require tweaks to avoid having the whole function removed. - Mem2Reg will generate variable & load/stores. This generates G_BITCAST in several cases. And there is currently something wrong we do with G_BITCAST which causes MIR verifier to complain. Until this is resolved, I disabled -verify-machineinstrs flag on those tests. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
22 lines
696 B
LLVM
22 lines
696 B
LLVM
; All OpVariable instructions in a function must be the first instructions in the first block
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; RUN: llc -O0 -mtriple=spirv32-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-linux %s -o - -filetype=obj | spirv-val %}
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; CHECK-SPIRV: OpFunction
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; CHECK-SPIRV-NEXT: OpLabel
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; CHECK-SPIRV-NEXT: OpVariable
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; CHECK-SPIRV-NEXT: OpVariable
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; CHECK-SPIRV: OpReturn
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; CHECK-SPIRV: OpFunctionEnd
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define void @main() #1 {
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entry:
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%0 = alloca <2 x i32>, align 4
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%1 = getelementptr <2 x i32>, ptr %0, i32 0, i32 0
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%2 = alloca float, align 4
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ret void
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}
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attributes #1 = { "hlsl.numthreads"="4,8,16" "hlsl.shader"="compute" }
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