67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
61 lines
2.2 KiB
LLVM
61 lines
2.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; CHECK-DAG: OpName [[FUN:%.+]] "fun"
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; CHECK-DAG: OpName [[FOO:%.+]] "foo"
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; CHECK-DAG: OpName [[GOO:%.+]] "goo"
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; CHECK-NOT: DAG-FENCE
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; CHECK-DAG: [[I16:%.+]] = OpTypeInt 16
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; CHECK-DAG: [[I32:%.+]] = OpTypeInt 32
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; CHECK-DAG: [[I64:%.+]] = OpTypeInt 64
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; CHECK-DAG: [[FN3:%.+]] = OpTypeFunction [[I32]] [[I32]] [[I16]] [[I64]]
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; CHECK-DAG: [[PAIR:%.+]] = OpTypeStruct [[I32]] [[I16]]
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; CHECK-DAG: [[FN1:%.+]] = OpTypeFunction [[I32]] [[I32]]
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; CHECK-DAG: [[FN2:%.+]] = OpTypeFunction [[I32]] [[PAIR]] [[I64]]
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;; According to the Specification, the OpUndef can be defined in Function.
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;; But the Specification also recommends defining it here. So we enforce that.
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; CHECK-DAG: [[UNDEF:%.+]] = OpUndef [[PAIR]]
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declare i32 @fun(i32 %value)
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;; Check for @fun declaration
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; CHECK: [[FUN]] = OpFunction [[I32]] None [[FN1]]
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; CHECK-NEXT: OpFunctionParameter [[I32]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @foo({i32, i16} %in, i64 %unused) {
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%first = extractvalue {i32, i16} %in, 0
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%bar = call i32 @fun(i32 %first)
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ret i32 %bar
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}
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; CHECK: [[GOO]] = OpFunction [[I32]] None [[FN3]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[I32]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[I16]]
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; CHECK-NEXT: [[C:%.+]] = OpFunctionParameter [[I64]]
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; CHECK: [[AGG1:%.+]] = OpCompositeInsert [[PAIR]] [[A]] [[UNDEF]] 0
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; CHECK: [[AGG2:%.+]] = OpCompositeInsert [[PAIR]] [[B]] [[AGG1]] 1
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; CHECK: [[RET:%.+]] = OpFunctionCall [[I32]] [[FOO]] [[AGG2]] [[C]]
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; CHECK: OpReturnValue [[RET]]
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; CHECK: OpFunctionEnd
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; CHECK: [[FOO]] = OpFunction [[I32]] None [[FN2]]
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; CHECK-NEXT: [[IN:%.+]] = OpFunctionParameter [[PAIR]]
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; CHECK-NEXT: OpFunctionParameter [[I64]]
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; CHECK: [[FIRST:%.+]] = OpCompositeExtract [[I32]] [[IN]] 0
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; CHECK: [[BAR:%.+]] = OpFunctionCall [[I32]] [[FUN]] [[FIRST]]
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; CHECK: OpReturnValue [[BAR]]
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; CHECK: OpFunctionEnd
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define i32 @goo(i32 %a, i16 %b, i64 %c) {
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%agg1 = insertvalue {i32, i16} undef, i32 %a, 0
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%agg2 = insertvalue {i32, i16} %agg1, i16 %b, 1
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%ret = call i32 @foo({i32, i16} %agg2, i64 %c)
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ret i32 %ret
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}
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;; TODO: test tailcall?
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