67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
212 lines
6.7 KiB
LLVM
212 lines
6.7 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "f32tof16"
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; CHECK-DAG: OpName [[EXT16_32:%.*]] "f16tof32"
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; CHECK-DAG: OpName [[TRUNC32_16v3:%.*]] "f32tof16v3"
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; CHECK-DAG: OpName [[EXT16_32v3:%.*]] "f16tof32v3"
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; CHECK-DAG: OpName [[F32toS32:%.*]] "f32tos32"
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; CHECK-DAG: OpName [[F32toS16:%.*]] "f32tos16"
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; CHECK-DAG: OpName [[F32toS8:%.*]] "f32tos8"
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; CHECK-DAG: OpName [[F16toS32:%.*]] "f16tos32"
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; CHECK-DAG: OpName [[F16toS16:%.*]] "f16tos16"
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; CHECK-DAG: OpName [[F16toS8:%.*]] "f16tos8"
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; CHECK-DAG: OpName [[F32toU32v2:%.*]] "f32tou32v2"
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; CHECK-DAG: OpName [[F32toU16v2:%.*]] "f32tou16v2"
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; CHECK-DAG: OpName [[F32toU8v2:%.*]] "f32tou8v2"
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; CHECK-DAG: OpName [[F16toU32v2:%.*]] "f16tou32v2"
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; CHECK-DAG: OpName [[F16toU16v2:%.*]] "f16tou16v2"
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; CHECK-DAG: OpName [[F16toU8v2:%.*]] "f16tou8v2"
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; CHECK-DAG: [[F32:%.*]] = OpTypeFloat 32
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; CHECK-DAG: [[F16:%.*]] = OpTypeFloat 16
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; CHECK-DAG: [[F32v2:%.*]] = OpTypeVector [[F32]] 2
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; CHECK-DAG: [[F16v2:%.*]] = OpTypeVector [[F16]] 2
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; CHECK-DAG: [[F32v3:%.*]] = OpTypeVector [[F32]] 3
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; CHECK-DAG: [[F16v3:%.*]] = OpTypeVector [[F16]] 3
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; CHECK-DAG: [[U32:%.*]] = OpTypeInt 32 0
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; CHECK-DAG: [[U16:%.*]] = OpTypeInt 16 0
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; CHECK-DAG: [[U8:%.*]] = OpTypeInt 8 0
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; CHECK-DAG: [[U32v2:%.*]] = OpTypeVector [[U32]] 2
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; CHECK-DAG: [[U16v2:%.*]] = OpTypeVector [[U16]] 2
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; CHECK-DAG: [[U8v2:%.*]] = OpTypeVector [[U8]] 2
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; CHECK: [[TRUNC32_16]] = OpFunction [[F16]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpFConvert [[F16]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define half @f32tof16(float %a) {
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%r = fptrunc float %a to half
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ret half %r
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}
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; CHECK: [[EXT16_32]] = OpFunction [[F32]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpFConvert [[F32]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define float @f16tof32(half %a) {
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%r = fpext half %a to float
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ret float %r
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}
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; CHECK: [[TRUNC32_16v3]] = OpFunction [[F16v3]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32v3]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpFConvert [[F16v3]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <3 x half> @f32tof16v3(<3 x float> %a) {
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%r = fptrunc <3 x float> %a to <3 x half>
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ret <3 x half> %r
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}
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; CHECK: [[EXT16_32v3]] = OpFunction [[F32v3]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16v3]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpFConvert [[F32v3]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <3 x float> @f16tof32v3(<3 x half> %a) {
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%r = fpext <3 x half> %a to <3 x float>
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ret <3 x float> %r
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}
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; CHECK: [[F32toS32]] = OpFunction [[U32]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToS [[U32]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @f32tos32(float %a) {
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%r = fptosi float %a to i32
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ret i32 %r
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}
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; CHECK: [[F32toS16]] = OpFunction [[U16]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToS [[U16]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i16 @f32tos16(float %a) {
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%r = fptosi float %a to i16
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ret i16 %r
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}
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; CHECK: [[F32toS8]] = OpFunction [[U8]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToS [[U8]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i8 @f32tos8(float %a) {
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%r = fptosi float %a to i8
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ret i8 %r
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}
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; CHECK: [[F16toS32]] = OpFunction [[U32]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToS [[U32]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @f16tos32(half %a) {
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%r = fptosi half %a to i32
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ret i32 %r
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}
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; CHECK: [[F16toS16]] = OpFunction [[U16]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToS [[U16]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i16 @f16tos16(half %a) {
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%r = fptosi half %a to i16
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ret i16 %r
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}
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; CHECK: [[F16toS8]] = OpFunction [[U8]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToS [[U8]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i8 @f16tos8(half %a) {
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%r = fptosi half %a to i8
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ret i8 %r
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}
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; CHECK: [[F32toU32v2]] = OpFunction [[U32v2]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32v2]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToU [[U32v2]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i32> @f32tou32v2(<2 x float> %a) {
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%r = fptoui <2 x float> %a to <2 x i32>
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ret <2 x i32> %r
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}
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; CHECK: [[F32toU16v2]] = OpFunction [[U16v2]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32v2]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToU [[U16v2]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i16> @f32tou16v2(<2 x float> %a) {
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%r = fptoui <2 x float> %a to <2 x i16>
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ret <2 x i16> %r
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}
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; CHECK: [[F32toU8v2]] = OpFunction [[U8v2]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F32v2]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToU [[U8v2]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i8> @f32tou8v2(<2 x float> %a) {
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%r = fptoui <2 x float> %a to <2 x i8>
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ret <2 x i8> %r
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}
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; CHECK: [[F16toU32v2]] = OpFunction [[U32v2]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16v2]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToU [[U32v2]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i32> @f16tou32v2(<2 x half> %a) {
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%r = fptoui <2 x half> %a to <2 x i32>
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ret <2 x i32> %r
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}
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; CHECK: [[F16toU16v2]] = OpFunction [[U16v2]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16v2]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToU [[U16v2]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i16> @f16tou16v2(<2 x half> %a) {
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%r = fptoui <2 x half> %a to <2 x i16>
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ret <2 x i16> %r
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}
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; CHECK: [[F16toU8v2]] = OpFunction [[U8v2]]
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; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16v2]]
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; CHECK: OpLabel
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; CHECK: [[R:%.*]] = OpConvertFToU [[U8v2]] [[A]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i8> @f16tou8v2(<2 x half> %a) {
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%r = fptoui <2 x half> %a to <2 x i8>
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ret <2 x i8> %r
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}
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