67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
96 lines
3.2 KiB
LLVM
96 lines
3.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; DISABLED-CHECK-DAG: OpName [[FNEG:%.+]] "scalar_fneg"
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; CHECK-DAG: OpName [[FADD:%.+]] "test_fadd"
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; CHECK-DAG: OpName [[FSUB:%.+]] "test_fsub"
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; CHECK-DAG: OpName [[FMUL:%.+]] "test_fmul"
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; CHECK-DAG: OpName [[FDIV:%.+]] "test_fdiv"
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; CHECK-DAG: OpName [[FREM:%.+]] "test_frem"
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; CHECK-DAG: OpName [[FMA:%.+]] "test_fma"
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; CHECK-DAG: [[F32Ty:%.+]] = OpTypeFloat 32
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; CHECK-DAG: [[FNTy:%.+]] = OpTypeFunction [[F32Ty]] [[F32Ty]] [[F32Ty]]
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; CHECK: [[FADD]] = OpFunction [[F32Ty]] None [[FNTy]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[C:%.+]] = OpFAdd [[F32Ty]] [[A]] [[B]]
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;; TODO: OpDecorate checks
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; CHECK-NEXT: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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define float @test_fadd(float %a, float %b) {
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%c = fadd nnan ninf float %a, %b
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ret float %c
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}
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; CHECK: [[FSUB]] = OpFunction [[F32Ty]] None [[FNTy]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[C:%.+]] = OpFSub [[F32Ty]] [[A]] [[B]]
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;; TODO: OpDecorate checks
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; CHECK-NEXT: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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define float @test_fsub(float %a, float %b) {
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%c = fsub fast float %a, %b
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ret float %c
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}
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; CHECK: [[FMUL]] = OpFunction [[F32Ty]] None [[FNTy]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[C:%.+]] = OpFMul [[F32Ty]] [[A]] [[B]]
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;; TODO: OpDecorate checks]
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; CHECK-NEXT: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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define float @test_fmul(float %a, float %b) {
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%c = fmul contract float %a, %b
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ret float %c
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}
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; CHECK: [[FDIV]] = OpFunction [[F32Ty]] None [[FNTy]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[C:%.+]] = OpFDiv [[F32Ty]] [[A]] [[B]]
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;; TODO: OpDecorate checks
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; CHECK-NEXT: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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define float @test_fdiv(float %a, float %b) {
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%c = fdiv arcp nsz float %a, %b
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ret float %c
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}
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; CHECK: [[FREM]] = OpFunction [[F32Ty]] None [[FNTy]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[C:%.+]] = OpFRem [[F32Ty]] [[A]] [[B]]
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;; TODO: OpDecorate checks
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; CHECK-NEXT: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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define float @test_frem(float %a, float %b) {
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%c = frem nsz float %a, %b
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ret float %c
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}
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declare float @llvm.fma.f32(float, float, float)
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; CHECK: [[FMA]] = OpFunction
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: [[C:%.+]] = OpFunctionParameter [[F32Ty]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: [[R:%.+]] = OpExtInst [[F32Ty]] {{%.+}} fma [[A]] [[B]] [[C]]
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;; TODO: OpDecorate checks
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; CHECK-NEXT: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define float @test_fma(float %a, float %b, float %c) {
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%r = call float @llvm.fma.f32(float %a, float %b, float %c)
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ret float %r
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}
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