6c32a1fdf7
Enable MachineCombining for FP add, sub and mul.
In order for this to work, the default instruction selection of reg/mem opcodes is disabled for ISD nodes that carry the flags that allow reassociation. The reg/mem folding is instead done after MachineCombiner by PeepholeOptimizer. SystemZInstrInfo optimizeLoadInstr() and foldMemoryOperandImpl() ("LoadMI version") have been implemented for this purpose also by this patch.
134 lines
3.7 KiB
LLVM
134 lines
3.7 KiB
LLVM
; Test 32-bit floating-point addition.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
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; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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declare float @foo()
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; Check register addition.
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define float @f1(float %f1, float %f2) {
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; CHECK-LABEL: f1:
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; CHECK: aebr %f0, %f2
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; CHECK: br %r14
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check the low end of the AEB range.
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define float @f2(float %f1, ptr %ptr) {
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; CHECK-LABEL: f2:
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; CHECK: aeb %f0, 0(%r2)
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; CHECK: br %r14
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%f2 = load float, ptr %ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check the high end of the aligned AEB range.
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define float @f3(float %f1, ptr %base) {
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; CHECK-LABEL: f3:
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; CHECK: aeb %f0, 4092(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, ptr %base, i64 1023
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%f2 = load float, ptr %ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define float @f4(float %f1, ptr %base) {
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; CHECK-LABEL: f4:
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; CHECK: aghi %r2, 4096
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; CHECK: aeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, ptr %base, i64 1024
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%f2 = load float, ptr %ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check negative displacements, which also need separate address logic.
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define float @f5(float %f1, ptr %base) {
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; CHECK-LABEL: f5:
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; CHECK: aghi %r2, -4
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; CHECK: aeb %f0, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr float, ptr %base, i64 -1
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%f2 = load float, ptr %ptr
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check that AEB allows indices.
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define float @f6(float %f1, ptr %base, i64 %index) {
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; CHECK-LABEL: f6:
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; CHECK: sllg %r1, %r3, 2
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; CHECK: aeb %f0, 400(%r1,%r2)
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; CHECK: br %r14
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%ptr1 = getelementptr float, ptr %base, i64 %index
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%ptr2 = getelementptr float, ptr %ptr1, i64 100
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%f2 = load float, ptr %ptr2
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%res = fadd float %f1, %f2
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ret float %res
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}
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; Check that additions of spilled values can use AEB rather than AEBR.
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define float @f7(ptr %ptr0) {
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; CHECK-LABEL: f7:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-SCALAR: aeb %f0, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr float, ptr %ptr0, i64 2
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%ptr2 = getelementptr float, ptr %ptr0, i64 4
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%ptr3 = getelementptr float, ptr %ptr0, i64 6
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%ptr4 = getelementptr float, ptr %ptr0, i64 8
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%ptr5 = getelementptr float, ptr %ptr0, i64 10
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%ptr6 = getelementptr float, ptr %ptr0, i64 12
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%ptr7 = getelementptr float, ptr %ptr0, i64 14
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%ptr8 = getelementptr float, ptr %ptr0, i64 16
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%ptr9 = getelementptr float, ptr %ptr0, i64 18
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%ptr10 = getelementptr float, ptr %ptr0, i64 20
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%val0 = load float, ptr %ptr0
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%val1 = load float, ptr %ptr1
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%val2 = load float, ptr %ptr2
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%val3 = load float, ptr %ptr3
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%val4 = load float, ptr %ptr4
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%val5 = load float, ptr %ptr5
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%val6 = load float, ptr %ptr6
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%val7 = load float, ptr %ptr7
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%val8 = load float, ptr %ptr8
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%val9 = load float, ptr %ptr9
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%val10 = load float, ptr %ptr10
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%ret = call float @foo()
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%add0 = fadd float %ret, %val0
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%add1 = fadd float %add0, %val1
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%add2 = fadd float %add1, %val2
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%add3 = fadd float %add2, %val3
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%add4 = fadd float %add3, %val4
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%add5 = fadd float %add4, %val5
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%add6 = fadd float %add5, %val6
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%add7 = fadd float %add6, %val7
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%add8 = fadd float %add7, %val8
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%add9 = fadd float %add8, %val9
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%add10 = fadd float %add9, %val10
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ret float %add10
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}
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; Check that reassociation flags do not get in the way of AEB.
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define float @f8(ptr %x) {
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; CHECK-LABEL: f8:
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; CHECK: aeb %f0
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entry:
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%0 = load float, ptr %x, align 8
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%arrayidx1 = getelementptr inbounds float, ptr %x, i64 1
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%1 = load float, ptr %arrayidx1, align 8
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%add = fadd reassoc nsz arcp contract afn float %1, %0
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ret float %add
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}
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