8424bf207e
This patch adds support for the next-generation arch15 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch15 as host processor. - Assembler/disassembler support for new instructions. - Exploitation of new instructions for code generation. - New vector (signed|unsigned|bool) __int128 data types. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10305. Note: No currently available Z system supports the arch15 architecture. Once new systems become available, the official system name will be added as supported -march name.
163 lines
4.7 KiB
LLVM
163 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
|
|
; Test 128-bit comparisons in vector registers on arch15
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 -verify-machineinstrs | FileCheck %s
|
|
|
|
; Equality comparison.
|
|
define i64 @f1(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vecq %v1, %v0
|
|
; CHECK-NEXT: selgre %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp eq i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Inequality comparison.
|
|
define i64 @f2(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vecq %v1, %v0
|
|
; CHECK-NEXT: selgrlh %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp ne i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Signed greater-than comparison.
|
|
define i64 @f3(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f3:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vecq %v1, %v0
|
|
; CHECK-NEXT: selgrh %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp sgt i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Signed less-than comparison.
|
|
define i64 @f4(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f4:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vecq %v1, %v0
|
|
; CHECK-NEXT: selgrl %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp slt i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Signed greater-or-equal comparison.
|
|
define i64 @f5(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f5:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vecq %v1, %v0
|
|
; CHECK-NEXT: selgrhe %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp sge i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Signed less-or-equal comparison.
|
|
define i64 @f6(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f6:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vecq %v1, %v0
|
|
; CHECK-NEXT: selgrle %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp sle i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Unsigned greater-than comparison.
|
|
define i64 @f7(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f7:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: veclq %v1, %v0
|
|
; CHECK-NEXT: selgrh %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp ugt i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Unsigned less-than comparison.
|
|
define i64 @f8(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: veclq %v1, %v0
|
|
; CHECK-NEXT: selgrl %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp ult i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Unsigned greater-or-equal comparison.
|
|
define i64 @f9(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f9:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: veclq %v1, %v0
|
|
; CHECK-NEXT: selgrhe %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp uge i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Unsigned less-or-equal comparison.
|
|
define i64 @f10(i128 %value1, i128 %value2, i64 %a, i64 %b) {
|
|
; CHECK-LABEL: f10:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: veclq %v1, %v0
|
|
; CHECK-NEXT: selgrle %r2, %r4, %r5
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp ule i128 %value1, %value2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|
|
|
|
; Select between i128 values.
|
|
define i128 @f11(i64 %value1, i64 %value2, i128 %a, i128 %b) {
|
|
; CHECK-LABEL: f11:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r5), 3
|
|
; CHECK-NEXT: cgrje %r3, %r4, .LBB10_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: vl %v1, 0(%r6), 3
|
|
; CHECK-NEXT: vaq %v0, %v0, %v1
|
|
; CHECK-NEXT: .LBB10_2:
|
|
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
|
; CHECK-NEXT: br %r14
|
|
%cond = icmp eq i64 %value1, %value2
|
|
%sum = add i128 %a, %b
|
|
%res = select i1 %cond, i128 %a, i128 %sum
|
|
ret i128 %res
|
|
}
|