8424bf207e
This patch adds support for the next-generation arch15 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch15 as host processor. - Assembler/disassembler support for new instructions. - Exploitation of new instructions for code generation. - New vector (signed|unsigned|bool) __int128 data types. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10305. Note: No currently available Z system supports the arch15 architecture. Once new systems become available, the official system name will be added as supported -march name.
117 lines
3.1 KiB
LLVM
117 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test i128 maximum on arch15.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
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; Test with slt.
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define i128 @f1(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vmxq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp slt i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with sle.
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define i128 @f2(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmxq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp sle i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with sgt.
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define i128 @f3(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmxq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp sgt i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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; Test with sge.
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define i128 @f4(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vmxq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp sge i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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; Test with ult.
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define i128 @f5(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vmxlq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp ult i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with ule.
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define i128 @f6(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmxlq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp ule i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with ugt.
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define i128 @f7(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmxlq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp ugt i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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; Test with uge.
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define i128 @f8(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vmxlq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp uge i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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