1bc8b3258e
This pull request port `regallocfast` to new pass manager. It exposes the parameter `filter` to handle different register classes for AMDGPU. IIUC AMDGPU need to allocate different register classes separately so it need implement its own `--<reg-class>-regalloc`. Now users can use e.g. `-passe=regallocfast<filter=sgpr>` to allocate specific register class. The command line option `--regalloc-npm` is still in work progress, plan to reuse the syntax of passes, e.g. use `--regalloc-npm=regallocfast<filter=sgpr>,greedy<filter=vgpr>` to replace `--sgpr-regalloc` and `--vgpr-regalloc`.
32 lines
999 B
YAML
32 lines
999 B
YAML
# RUN: llc -verify-machineinstrs -run-pass regallocfast -mtriple s390x-ibm-linux -o - %s | FileCheck %s
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# RUN: llc -verify-machineinstrs -passes=regallocfast -mtriple s390x-ibm-linux -o - %s | FileCheck %s
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--- |
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@g_167 = external global [5 x i64], align 8
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define void @main() local_unnamed_addr {
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ret void
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}
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...
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# Make sure the usage of different subregisters on the same virtual register
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# does not result in invalid kill flags.
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# PR33677
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---
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name: main
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alignment: 4
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tracksRegLiveness: true
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# CHECK: $r0l = COPY renamable $r1l
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# Although R0L partially redefines R0Q, it must not mark R0Q as kill
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# because R1D is still live through that instruction.
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# CHECK-NOT: implicit killed $r0q
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# CHECK-NEXT: {{\$r[0-9]+d}} = COPY renamable $r1d
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# CHECK-NEXT: LARL
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body: |
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bb.0:
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%0 : gr128bit = IMPLICIT_DEF
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%0.subreg_l32 = COPY %0.subreg_ll32
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%1 : gr64bit = COPY %0.subreg_l64
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%2 : addr64bit = LARL @g_167
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STC %1.subreg_l32, %2, 8, $noreg
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...
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