6c331e50e4
Per the discussion in #102542, it is safe to insert BBs under `lowerIntrinsics()` since #69535 has made tolerant of modifying BBs. So, I can get rid of using the inlined function `rmw_or`, introduced in #96040.
61 lines
3.1 KiB
LLVM
61 lines
3.1 KiB
LLVM
; Check that MC/DC intrinsics are properly lowered
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; RUN: opt < %s -passes=instrprof -S | FileCheck %s --check-prefixes=CHECK,BASIC
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; RUN: opt < %s -passes=instrprof -S -instrprof-atomic-counter-update-all | FileCheck %s --check-prefixes=CHECK,ATOMIC
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; RUN: opt < %s -passes=instrprof -S -runtime-counter-relocation | FileCheck %s --check-prefixes=CHECK,RELOC
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target triple = "x86_64-unknown-linux-gnu"
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@__profn_test = private constant [4 x i8] c"test"
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; BASIC: [[PROFBM_ADDR:@__profbm_test]] = private global [1 x i8] zeroinitializer, section "__llvm_prf_bits", comdat, align 1
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; ATOMIC: [[PROFBM_ADDR:@__profbm_test]] = private global [1 x i8] zeroinitializer, section "__llvm_prf_bits", comdat, align 1
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define dso_local void @test(i32 noundef %A) {
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entry:
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; RELOC: %profbm_bias = load i64, ptr @__llvm_profile_bitmap_bias, align [[#]], !invariant.load !0
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; RELOC: %profc_bias = load i64, ptr @__llvm_profile_counter_bias, align [[#]]
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%A.addr = alloca i32, align 4
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%mcdc.addr = alloca i32, align 4
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call void @llvm.instrprof.cover(ptr @__profn_test, i64 99278, i32 5, i32 0)
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; BASIC: store i8 0, ptr @__profc_test, align 1
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; RELOC: %[[PROFC_INTADDR:.+]] = add i64 ptrtoint (ptr @__profc_test to i64), %profc_bias
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; RELOC: %[[PROFC_ADDR:.+]] = inttoptr i64 %[[PROFC_INTADDR]] to ptr
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; RELOC: store i8 0, ptr %[[PROFC_ADDR]], align 1
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call void @llvm.instrprof.mcdc.parameters(ptr @__profn_test, i64 99278, i32 1)
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store i32 0, ptr %mcdc.addr, align 4
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%0 = load i32, ptr %A.addr, align 4
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%tobool = icmp ne i32 %0, 0
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call void @llvm.instrprof.mcdc.tvbitmap.update(ptr @__profn_test, i64 99278, i32 0, ptr %mcdc.addr)
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; RELOC: [[PROFBM_ADDR:%.+]] = getelementptr i8, ptr @__profbm_test, i64 %profbm_bias
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; CHECK: %[[TEMP0:mcdc.*]] = load i32, ptr %mcdc.addr, align 4
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; CHECK-NEXT: %[[TEMP:[0-9]+]] = add i32 %[[TEMP0]], 0
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; CHECK-NEXT: %[[LAB4:[0-9]+]] = lshr i32 %[[TEMP]], 3
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; CHECK-NEXT: %[[LAB7:[0-9]+]] = getelementptr inbounds i8, ptr [[PROFBM_ADDR]], i32 %[[LAB4]]
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; CHECK-NEXT: %[[LAB8:[0-9]+]] = and i32 %[[TEMP]], 7
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; CHECK-NEXT: %[[LAB9:[0-9]+]] = trunc i32 %[[LAB8]] to i8
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; CHECK-NEXT: %[[LAB10:[0-9]+]] = shl i8 1, %[[LAB9]]
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; CHECK-NEXT: %[[BITS:.+]] = load i8, ptr %[[LAB7]], align 1
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; ATOMIC-NEXT: %[[MASKED:.+]] = and i8 %[[BITS]], %[[LAB10]]
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; ATOMIC-NEXT: %[[SHOULDWRITE:.+]] = icmp ne i8 %[[MASKED]], %[[LAB10]]
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; ATOMIC-NEXT: br i1 %[[SHOULDWRITE]], label %[[WRITE:.+]], label %[[SKIP:.+]], !prof ![[MDPROF:[0-9]+]]
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; ATOMIC: [[WRITE]]:
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; BASIC-NEXT: %[[LAB11:[0-9]+]] = or i8 %[[BITS]], %[[LAB10]]
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; RELOC-NEXT: %[[LAB11:[0-9]+]] = or i8 %[[BITS]], %[[LAB10]]
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; BASIC-NEXT: store i8 %[[LAB11]], ptr %[[LAB7]], align 1
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; RELOC-NEXT: store i8 %[[LAB11]], ptr %[[LAB7]], align 1
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; ATOMIC-NEXT: %{{.+}} = atomicrmw or ptr %[[LAB7]], i8 %[[LAB10]] monotonic, align 1
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; ATOMIC: [[SKIP]]:
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ret void
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; CHECK-NEXT: ret void
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}
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; ATOMIC: ![[MDPROF]] = !{!"branch_weights", i32 1, i32 1048575}
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declare void @llvm.instrprof.cover(ptr, i64, i32, i32)
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declare void @llvm.instrprof.mcdc.parameters(ptr, i64, i32)
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declare void @llvm.instrprof.mcdc.tvbitmap.update(ptr, i64, i32, ptr)
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