094572701d
This patch makes the final major change of the RemoveDIs project, changing the default IR output from debug intrinsics to debug records. This is expected to break a large number of tests: every single one that tests for uses or declarations of debug intrinsics and does not explicitly disable writing records. If this patch has broken your downstream tests (or upstream tests on a configuration I wasn't able to run): 1. If you need to immediately unblock a build, pass `--write-experimental-debuginfo=false` to LLVM's option processing for all failing tests (remember to use `-mllvm` for clang/flang to forward arguments to LLVM). 2. For most test failures, the changes are trivial and mechanical, enough that they can be done by script; see the migration guide for a guide on how to do this: https://llvm.org/docs/RemoveDIsDebugInfo.html#test-updates 3. If any tests fail for reasons other than FileCheck check lines that need updating, such as assertion failures, that is most likely a real bug with this patch and should be reported as such. For more information, see the recent PSA: https://discourse.llvm.org/t/psa-ir-output-changing-from-debug-intrinsics-to-debug-records/79578
72 lines
4.1 KiB
LLVM
72 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=debugify,loop-idiom,verify -pass-remarks=loop-idiom -pass-remarks-analysis=loop-idiom -pass-remarks-output=%t.yaml -verify-each -verify-dom-info -verify-loop-info < %s -S 2>&1 | FileCheck %s
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; RUN: FileCheck --input-file=%t.yaml %s --check-prefixes=YAML
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; RUN: opt -passes=debugify,loop-idiom,verify -pass-remarks=loop-idiom -pass-remarks-analysis=loop-idiom -pass-remarks-output=%t.yaml -verify-each -verify-dom-info -verify-loop-info < %s -S 2>&1 --try-experimental-debuginfo-iterators | FileCheck %s
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; RUN: FileCheck --input-file=%t.yaml %s --check-prefixes=YAML
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Check that everything still works when debuginfo is present, and that it is reasonably propagated.
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; CHECK: remark: <stdin>:6:1: Formed a call to llvm.memcpy.p0.p0.i64() intrinsic from load and store instruction in test6_dest_align function{{$}}
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; YAML: --- !Passed
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; YAML-NEXT: Pass: loop-idiom
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; YAML-NEXT: Name: ProcessLoopStoreOfLoopLoad
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; YAML-NEXT: DebugLoc: { File: '<stdin>', Line: 6, Column: 1 }
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; YAML-NEXT: Function: test6_dest_align
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; YAML-NEXT: Args:
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; YAML-NEXT: - String: 'Formed a call to '
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; YAML-NEXT: - NewFunction: llvm.memcpy.p0.p0.i64
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; YAML-NEXT: - String: '() intrinsic from '
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; YAML-NEXT: - Inst: load and store
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; YAML-NEXT: - String: ' instruction in '
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; YAML-NEXT: - Function: test6_dest_align
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; YAML-NEXT: DebugLoc: { File: '<stdin>', Line: 1, Column: 0 }
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; YAML-NEXT: - String: ' function'
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; YAML-NEXT: - FromBlock: for.body
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; YAML-NEXT: - ToBlock: bb.nph
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; YAML-NEXT: ...
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define void @test6_dest_align(ptr noalias align 1 %Base, ptr noalias align 4 %Dest, i64 %Size) nounwind ssp {
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; CHECK-LABEL: @test6_dest_align(
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; CHECK-NEXT: bb.nph:
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; CHECK-NEXT: [[TMP0:%.*]] = shl nuw i64 [[SIZE:%.*]], 2, !dbg [[DBG18:![0-9]+]]
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; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[DEST:%.*]], ptr align 1 [[BASE:%.*]], i64 [[TMP0]], i1 false), !dbg [[DBG19:![0-9]+]]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]], !dbg [[DBG18]]
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; CHECK: for.body:
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; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[BB_NPH:%.*]] ], [ [[INDVAR_NEXT:%.*]], [[FOR_BODY]] ], !dbg [[DBG20:![0-9]+]]
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; CHECK-NEXT: #dbg_value(i64 [[INDVAR]], [[META9:![0-9]+]], !DIExpression(), [[DBG20]])
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; CHECK-NEXT: [[I_0_014:%.*]] = getelementptr i32, ptr [[BASE]], i64 [[INDVAR]], !dbg [[DBG21:![0-9]+]]
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; CHECK-NEXT: #dbg_value(ptr [[I_0_014]], [[META11:![0-9]+]], !DIExpression(), [[DBG21]])
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; CHECK-NEXT: [[DESTI:%.*]] = getelementptr i32, ptr [[DEST]], i64 [[INDVAR]], !dbg [[DBG22:![0-9]+]]
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; CHECK-NEXT: #dbg_value(ptr [[DESTI]], [[META12:![0-9]+]], !DIExpression(), [[DBG22]])
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; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[I_0_014]], align 1, !dbg [[DBG23:![0-9]+]]
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; CHECK-NEXT: #dbg_value(i32 [[V]], [[META13:![0-9]+]], !DIExpression(), [[DBG23]])
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; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1, !dbg [[DBG24:![0-9]+]]
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; CHECK-NEXT: #dbg_value(i64 [[INDVAR_NEXT]], [[META15:![0-9]+]], !DIExpression(), [[DBG24]])
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVAR_NEXT]], [[SIZE]], !dbg [[DBG25:![0-9]+]]
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; CHECK-NEXT: #dbg_value(i1 [[EXITCOND]], [[META16:![0-9]+]], !DIExpression(), [[DBG25]])
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]], !dbg [[DBG26:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void, !dbg [[DBG27:![0-9]+]]
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;
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bb.nph:
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br label %for.body
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for.body: ; preds = %bb.nph, %for.body
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%indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ]
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%I.0.014 = getelementptr i32, ptr %Base, i64 %indvar
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%DestI = getelementptr i32, ptr %Dest, i64 %indvar
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%V = load i32, ptr %I.0.014, align 1
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store i32 %V, ptr %DestI, align 4
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%indvar.next = add i64 %indvar, 1
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%exitcond = icmp eq i64 %indvar.next, %Size
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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