3097c60928
Currently it's very difficult to improve the cost model for tail-folded loops because as soon as you add a VPInstruction::computeCost function that adds the costs of instructions such as VPInstruction::ActiveLaneMask and VPInstruction::ExplicitVectorLength the assert in LoopVectorizationPlanner::computeBestVF fails for some tests. This is because the VF chosen by the legacy cost model doesn't match the vplan cost model. See PR #90191. This assert is currently making it difficult to improve the cost model. Hopefully we will be in a position to remove the assert soon, however in order to do that we have to fix up a whole bunch of tests that rely upon the legacy cost model output. I've tried my best to update these tests to use vplan output instead. There is still work needed for the VF=1 case because the vplan cost model is not printed out in this case. I've not attempted to fix those in this patch.
87 lines
4.3 KiB
LLVM
87 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; REQUIRES: asserts
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; RUN: opt < %s -passes=loop-vectorize -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s --check-prefix=COST
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; RUN: opt < %s -passes=loop-vectorize,instcombine,simplifycfg -force-vector-width=2 -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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; This test checks that we correctly compute the scalarized operands for a
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; user-specified vectorization factor when interleaving is disabled. We use the
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; "optsize" attribute to disable all interleaving calculations. A cost of 4
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; for %var4 indicates that we would scalarize it's operand (%var3), giving
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; %var4 a lower scalarization overhead.
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;
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; COST-LABEL: predicated_udiv_scalarized_operand
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; COST: Cost of 5 for VF 2: profitable to scalarize %var4 = udiv i64 %var2, %var3
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;
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;
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define i64 @predicated_udiv_scalarized_operand(ptr %a, i64 %x) optsize {
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; CHECK-LABEL: @predicated_udiv_scalarized_operand(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_UDIV_CONTINUE2:%.*]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY]] ], [ [[TMP17:%.*]], [[PRED_UDIV_CONTINUE2]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <2 x i64> [[WIDE_LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i64 0
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; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_UDIV_IF:%.*]], label [[PRED_UDIV_CONTINUE:%.*]]
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; CHECK: pred.udiv.if:
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 0
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; CHECK-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], [[X:%.*]]
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 0
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; CHECK-NEXT: [[TMP7:%.*]] = udiv i64 [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[TMP7]], i64 0
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; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE]]
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; CHECK: pred.udiv.continue:
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; CHECK-NEXT: [[TMP9:%.*]] = phi <2 x i64> [ poison, [[VECTOR_BODY]] ], [ [[TMP8]], [[PRED_UDIV_IF]] ]
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP2]], i64 1
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; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_UDIV_IF1:%.*]], label [[PRED_UDIV_CONTINUE2]]
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; CHECK: pred.udiv.if1:
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; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 1
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; CHECK-NEXT: [[TMP12:%.*]] = add nsw i64 [[TMP11]], [[X]]
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; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 1
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; CHECK-NEXT: [[TMP14:%.*]] = udiv i64 [[TMP13]], [[TMP12]]
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; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i64> [[TMP9]], i64 [[TMP14]], i64 1
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; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE2]]
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; CHECK: pred.udiv.continue2:
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; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x i64> [ [[TMP9]], [[PRED_UDIV_CONTINUE]] ], [ [[TMP15]], [[PRED_UDIV_IF1]] ]
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; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP2]], <2 x i64> [[TMP16]], <2 x i64> [[WIDE_LOAD]]
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; CHECK-NEXT: [[TMP17]] = add <2 x i64> [[VEC_PHI]], [[PREDPHI]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[TMP17]])
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; CHECK-NEXT: ret i64 [[TMP19]]
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;
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
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%r = phi i64 [ 0, %entry ], [ %var6, %for.inc ]
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%var0 = getelementptr inbounds i64, ptr %a, i64 %i
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%var2 = load i64, ptr %var0, align 4
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%cond0 = icmp sgt i64 %var2, 0
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br i1 %cond0, label %if.then, label %for.inc
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if.then:
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%var3 = add nsw i64 %var2, %x
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%var4 = udiv i64 %var2, %var3
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br label %for.inc
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for.inc:
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%var5 = phi i64 [ %var2, %for.body ], [ %var4, %if.then]
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%var6 = add i64 %r, %var5
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%i.next = add nuw nsw i64 %i, 1
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%cond1 = icmp slt i64 %i.next, 100
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br i1 %cond1, label %for.body, label %for.end
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for.end:
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%var7 = phi i64 [ %var6, %for.inc ]
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ret i64 %var7
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}
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