a105877646
The idea behind this canonicalization is that it allows us to handle less patterns, because we know that some will be canonicalized away. This is indeed very useful to e.g. know that constants are always on the right. However, this is only useful if the canonicalization is actually reliable. This is the case for constants, but not for arguments: Moving these to the right makes it look like the "more complex" expression is guaranteed to be on the left, but this is not actually the case in practice. It fails as soon as you replace the argument with another instruction. The end result is that it looks like things correctly work in tests, while they actually don't. We use the "thwart complexity-based canonicalization" trick to handle this in tests, but it's often a challenge for new contributors to get this right, and based on the regressions this PR originally exposed, we clearly don't get this right in many cases. For this reason, I think that it's better to remove this complexity canonicalization. It will make it much easier to write tests for commuted cases and make sure that they are handled.
120 lines
4.0 KiB
LLVM
120 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='default<Os>' -S %s | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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declare void @use(i16)
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define void @test_remove_check_with_incrementing_integer_induction(i16 %start, i8 %len.n, i16 %a) {
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; CHECK-LABEL: @test_remove_check_with_incrementing_integer_induction(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LEN:%.*]] = zext i8 [[LEN_N:%.*]] to i16
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; CHECK-NEXT: [[LEN_NEG_NOT:%.*]] = icmp ugt i16 [[A:%.*]], [[LEN]]
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; CHECK-NEXT: [[C1:%.*]] = icmp ne i8 [[LEN_N]], 0
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; CHECK-NEXT: [[OR_COND3:%.*]] = and i1 [[LEN_NEG_NOT]], [[C1]]
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; CHECK-NEXT: br i1 [[OR_COND3]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.latch.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[A]], -1
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; CHECK-NEXT: [[TMP1:%.*]] = add nsw i16 [[LEN]], -1
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; CHECK-NEXT: [[UMIN:%.*]] = tail call i16 @llvm.umin.i16(i16 [[TMP0]], i16 [[TMP1]])
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[IV2:%.*]] = phi i16 [ [[IV_NEXT:%.*]], [[LOOP_LATCH]] ], [ 0, [[LOOP_LATCH_PREHEADER]] ]
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; CHECK-NEXT: tail call void @use(i16 [[IV2]])
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i16 [[IV2]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i16 [[IV2]], [[UMIN]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[EXIT]], label [[LOOP_LATCH]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%len = zext i8 %len.n to i16
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%upper = add nuw nsw i16 %start, %len
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%len.neg = icmp uge i16 %len, %a
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br i1 %len.neg, label %exit, label %loop.ph
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loop.ph:
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br label %loop.header
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loop.header:
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%iv = phi i16 [ 0, %loop.ph ], [ %iv.next, %loop.latch ]
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%c = icmp eq i16 %iv, %len
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br i1 %c, label %exit, label %for.body
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for.body:
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%t.1 = icmp uge i16 %iv, 0
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%t.2 = icmp ult i16 %iv, %a
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%and = and i1 %t.1, %t.2
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br i1 %and, label %loop.latch, label %exit
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loop.latch:
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call void @use(i16 %iv)
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%iv.next = add nuw nsw i16 %iv, 1
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br label %loop.header
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exit:
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ret void
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}
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define void @chained_conditions(i64 noundef %a, i64 noundef %b, i64 noundef %c, i64 noundef %d) #0 {
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; CHECK-LABEL: @chained_conditions(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret void
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;
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entry:
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%a.addr = alloca i64, align 8
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%b.addr = alloca i64, align 8
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%c.addr = alloca i64, align 8
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%d.addr = alloca i64, align 8
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store i64 %a, ptr %a.addr, align 8
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store i64 %b, ptr %b.addr, align 8
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store i64 %c, ptr %c.addr, align 8
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store i64 %d, ptr %d.addr, align 8
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%0 = load i64, ptr %a.addr, align 8
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%cmp = icmp ugt i64 %0, 2048
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br i1 %cmp, label %if.then, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%1 = load i64, ptr %b.addr, align 8
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%cmp1 = icmp ugt i64 %1, 1024
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br i1 %cmp1, label %if.then, label %lor.lhs.false2
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lor.lhs.false2: ; preds = %lor.lhs.false
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%2 = load i64, ptr %c.addr, align 8
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%cmp3 = icmp ugt i64 %2, 1024
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br i1 %cmp3, label %if.then, label %if.end
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if.then: ; preds = %lor.lhs.false2, %lor.lhs.false, %entry
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br label %if.end10
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if.end: ; preds = %lor.lhs.false2
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%3 = load i64, ptr %a.addr, align 8
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%4 = load i64, ptr %b.addr, align 8
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%add = add i64 %3, %4
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%5 = load i64, ptr %c.addr, align 8
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%add4 = add i64 %add, %5
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%6 = load i64, ptr %d.addr, align 8
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%cmp5 = icmp uge i64 %add4, %6
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br i1 %cmp5, label %if.then6, label %if.end7
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if.then6: ; preds = %if.end
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br label %if.end10
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if.end7: ; preds = %if.end
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%7 = load i64, ptr %a.addr, align 8
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%8 = load i64, ptr %d.addr, align 8
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%cmp8 = icmp uge i64 %7, %8
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br i1 %cmp8, label %if.then9, label %if.end10
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if.then9: ; preds = %if.end7
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call void @bar()
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br label %if.end10
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if.end10: ; preds = %if.then, %if.then6, %if.then9, %if.end7
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ret void
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}
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declare void @bar()
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