f00f294130
Still need to do the full analysis of the signedness of the values rather than rely on Instruction opcode, if the opcode is SExt. Still may produce unsigned result.
28 lines
1003 B
LLVM
28 lines
1003 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -mtriple=aarch64 -passes=slp-vectorizer -S -slp-threshold=-100 < %s | FileCheck %s
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define i16 @test() {
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; CHECK-LABEL: define i16 @test() {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LNOT:%.*]] = xor i1 true, true
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; CHECK-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[LNOT]] to i16
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i16 0, [[LNOT_EXT]]
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; CHECK-NEXT: [[LNOT5:%.*]] = xor i1 true, true
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; CHECK-NEXT: [[LNOT_EXT6:%.*]] = zext i1 [[LNOT5]] to i16
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; CHECK-NEXT: [[ADD7:%.*]] = add nsw i16 [[ADD]], [[LNOT_EXT6]]
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; CHECK-NEXT: ret i16 [[ADD7]]
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;
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entry:
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%conv = sext i16 1 to i32
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%cmp = icmp eq i32 %conv, 1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i16
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%add = add nsw i16 0, %lnot.ext
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%conv2 = sext i16 1 to i32
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%cmp3 = icmp eq i32 %conv2, 1
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%lnot5 = xor i1 %cmp3, true
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%lnot.ext6 = zext i1 %lnot5 to i16
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%add7 = add nsw i16 %add, %lnot.ext6
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ret i16 %add7
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}
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