a4aa6bc8fc
If the operand node has the same scalars as one of the vectorized nodes, the compiler could miss this and incorrectly request minbitwidth data for the wrong node. It may lead to a compiler crash, because the vectorized node might have different minbw result. Fixes https://github.com/llvm/llvm-project/issues/106667
45 lines
1.8 KiB
LLVM
45 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define void @test(ptr %p) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 16
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; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr [[GEP1]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%conv548.2.i.13 = zext i32 0 to i64
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%and551.2.i.13 = and i64 0, %conv548.2.i.13
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%conv548.3.i.13 = zext i32 0 to i64
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%and551.3.i.13 = and i64 0, %conv548.3.i.13
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%0 = trunc i64 %and551.2.i.13 to i32
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%conv54.2.i.14 = and i32 %0, 0
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%conv548.2.i.14 = zext i32 %conv54.2.i.14 to i64
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%and551.2.i.14 = and i64 %and551.2.i.13, %conv548.2.i.14
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%1 = trunc i64 %and551.3.i.13 to i32
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%conv54.3.i.14 = and i32 %1, 0
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%conv548.3.i.14 = zext i32 %conv54.3.i.14 to i64
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%and551.3.i.14 = and i64 %and551.3.i.13, %conv548.3.i.14
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%and551.2.i.15 = and i64 %and551.2.i.14, 0
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%and551.3.i.15 = and i64 %and551.3.i.14, 0
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%and551.2.i.16 = and i64 %and551.2.i.15, 0
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%and551.3.i.16 = and i64 %and551.3.i.15, 0
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%and551.2.i.17 = and i64 %and551.2.i.16, 0
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%and551.3.i.17 = and i64 %and551.3.i.16, 0
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%and551.2.i.18 = and i64 %and551.2.i.17, 0
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%and551.3.i.18 = and i64 %and551.3.i.17, 0
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%and551.2.i.19 = and i64 %and551.2.i.18, 0
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%and551.3.i.19 = and i64 %and551.3.i.18, 0
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%and551.2.i.20 = and i64 %and551.2.i.19, 0
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%and551.3.i.20 = and i64 %and551.3.i.19, 0
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%and551.2.i.21 = and i64 %and551.2.i.20, 0
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%and551.3.i.21 = and i64 %and551.3.i.20, 0
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%gep1 = getelementptr inbounds i8, ptr %p, i64 16
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%gep2 = getelementptr inbounds i8, ptr %p, i64 24
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store i64 %and551.2.i.21, ptr %gep1, align 16
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store i64 %and551.3.i.21, ptr %gep2, align 8
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ret void
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}
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