9cbc1f29ca
In the LLVM style guide, we prefer not using braced initializer lists to call a constructor. Also, we prefer using an equal before the open curly brace if we use a braced initializer list when initializing a variable. See https://llvm.org/docs/CodingStandards.html#do-not-use-braced-initializer-lists-to-call-a-constructor for more details. The style guide does not explain the reason well. There is an article from abseil, which mentions few benefits. E.g., we can avoid the most vexing parse, etc. See https://abseil.io/tips/88 for more details. Signed-off-by: hanhanW <hanhan0912@gmail.com>
292 lines
13 KiB
C++
292 lines
13 KiB
C++
//===- AVXTranspose.cpp - Lower Vector transpose to AVX -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements vector.transpose rewrites as AVX patterns for particular
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// sizes of interest.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/Arith/IR/Arith.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/Vector/IR/VectorOps.h"
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#include "mlir/Dialect/Vector/Utils/VectorUtils.h"
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#include "mlir/Dialect/X86Vector/Transforms.h"
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#include "mlir/IR/ImplicitLocOpBuilder.h"
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#include "mlir/IR/Matchers.h"
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#include "mlir/IR/PatternMatch.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/FormatVariadic.h"
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using namespace mlir;
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using namespace mlir::vector;
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using namespace mlir::x86vector;
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using namespace mlir::x86vector::avx2;
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using namespace mlir::x86vector::avx2::inline_asm;
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using namespace mlir::x86vector::avx2::intrin;
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Value mlir::x86vector::avx2::inline_asm::mm256BlendPsAsm(
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ImplicitLocOpBuilder &b, Value v1, Value v2, uint8_t mask) {
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auto asmDialectAttr =
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LLVM::AsmDialectAttr::get(b.getContext(), LLVM::AsmDialect::AD_Intel);
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const auto *asmTp = "vblendps $0, $1, $2, {0}";
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const auto *asmCstr =
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"=x,x,x"; // Careful: constraint parser is very brittle: no ws!
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SmallVector<Value> asmVals{v1, v2};
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auto asmStr = llvm::formatv(asmTp, llvm::format_hex(mask, /*width=*/2)).str();
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auto asmOp = b.create<LLVM::InlineAsmOp>(
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v1.getType(), /*operands=*/asmVals, /*asm_string=*/asmStr,
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/*constraints=*/asmCstr, /*has_side_effects=*/false,
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/*is_align_stack=*/false, /*asm_dialect=*/asmDialectAttr,
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/*operand_attrs=*/ArrayAttr());
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return asmOp.getResult(0);
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}
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Value mlir::x86vector::avx2::intrin::mm256UnpackLoPs(ImplicitLocOpBuilder &b,
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Value v1, Value v2) {
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return b.create<vector::ShuffleOp>(
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v1, v2, ArrayRef<int64_t>{0, 8, 1, 9, 4, 12, 5, 13});
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}
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Value mlir::x86vector::avx2::intrin::mm256UnpackHiPs(ImplicitLocOpBuilder &b,
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Value v1, Value v2) {
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return b.create<vector::ShuffleOp>(
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v1, v2, ArrayRef<int64_t>{2, 10, 3, 11, 6, 14, 7, 15});
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}
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/// a a b b a a b b
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/// Takes an 8 bit mask, 2 bit for each position of a[0, 3) **and** b[0, 4):
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/// 0:127 | 128:255
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/// b01 b23 C8 D8 | b01+4 b23+4 C8+4 D8+4
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Value mlir::x86vector::avx2::intrin::mm256ShufflePs(ImplicitLocOpBuilder &b,
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Value v1, Value v2,
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uint8_t mask) {
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uint8_t b01, b23, b45, b67;
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MaskHelper::extractShuffle(mask, b01, b23, b45, b67);
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SmallVector<int64_t> shuffleMask = {
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b01, b23, b45 + 8, b67 + 8, b01 + 4, b23 + 4, b45 + 8 + 4, b67 + 8 + 4};
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return b.create<vector::ShuffleOp>(v1, v2, shuffleMask);
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}
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// imm[0:1] out of imm[0:3] is:
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// 0 1 2 3
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// a[0:127] or a[128:255] or b[0:127] or b[128:255] |
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// a[0:127] or a[128:255] or b[0:127] or b[128:255]
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// 0 1 2 3
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// imm[0:1] out of imm[4:7].
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Value mlir::x86vector::avx2::intrin::mm256Permute2f128Ps(
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ImplicitLocOpBuilder &b, Value v1, Value v2, uint8_t mask) {
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SmallVector<int64_t> shuffleMask;
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auto appendToMask = [&](uint8_t control) {
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if (control == 0)
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llvm::append_range(shuffleMask, ArrayRef<int64_t>{0, 1, 2, 3});
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else if (control == 1)
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llvm::append_range(shuffleMask, ArrayRef<int64_t>{4, 5, 6, 7});
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else if (control == 2)
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llvm::append_range(shuffleMask, ArrayRef<int64_t>{8, 9, 10, 11});
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else if (control == 3)
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llvm::append_range(shuffleMask, ArrayRef<int64_t>{12, 13, 14, 15});
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else
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llvm_unreachable("control > 3 : overflow");
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};
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uint8_t b03, b47;
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MaskHelper::extractPermute(mask, b03, b47);
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appendToMask(b03);
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appendToMask(b47);
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return b.create<vector::ShuffleOp>(v1, v2, shuffleMask);
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}
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/// If bit i of `mask` is zero, take f32@i from v1 else take it from v2.
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Value mlir::x86vector::avx2::intrin::mm256BlendPs(ImplicitLocOpBuilder &b,
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Value v1, Value v2,
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uint8_t mask) {
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SmallVector<int64_t, 8> shuffleMask;
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for (int i = 0; i < 8; ++i) {
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bool isSet = mask & (1 << i);
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shuffleMask.push_back(!isSet ? i : i + 8);
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}
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return b.create<vector::ShuffleOp>(v1, v2, shuffleMask);
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}
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/// AVX2 4x8xf32-specific transpose lowering using a "C intrinsics" model.
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void mlir::x86vector::avx2::transpose4x8xf32(ImplicitLocOpBuilder &ib,
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MutableArrayRef<Value> vs) {
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#ifndef NDEBUG
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auto vt = VectorType::get({8}, Float32Type::get(ib.getContext()));
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assert(vs.size() == 4 && "expects 4 vectors");
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assert(llvm::all_of(ValueRange{vs}.getTypes(),
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[&](Type t) { return t == vt; }) &&
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"expects all types to be vector<8xf32>");
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#endif
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Value t0 = mm256UnpackLoPs(ib, vs[0], vs[1]);
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Value t1 = mm256UnpackHiPs(ib, vs[0], vs[1]);
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Value t2 = mm256UnpackLoPs(ib, vs[2], vs[3]);
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Value t3 = mm256UnpackHiPs(ib, vs[2], vs[3]);
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Value s0 = mm256ShufflePs(ib, t0, t2, MaskHelper::shuffle<1, 0, 1, 0>());
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Value s1 = mm256ShufflePs(ib, t0, t2, MaskHelper::shuffle<3, 2, 3, 2>());
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Value s2 = mm256ShufflePs(ib, t1, t3, MaskHelper::shuffle<1, 0, 1, 0>());
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Value s3 = mm256ShufflePs(ib, t1, t3, MaskHelper::shuffle<3, 2, 3, 2>());
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vs[0] = mm256Permute2f128Ps(ib, s0, s1, MaskHelper::permute<2, 0>());
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vs[1] = mm256Permute2f128Ps(ib, s2, s3, MaskHelper::permute<2, 0>());
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vs[2] = mm256Permute2f128Ps(ib, s0, s1, MaskHelper::permute<3, 1>());
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vs[3] = mm256Permute2f128Ps(ib, s2, s3, MaskHelper::permute<3, 1>());
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}
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/// AVX2 8x8xf32-specific transpose lowering using a "C intrinsics" model.
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void mlir::x86vector::avx2::transpose8x8xf32(ImplicitLocOpBuilder &ib,
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MutableArrayRef<Value> vs) {
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auto vt = VectorType::get({8}, Float32Type::get(ib.getContext()));
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(void)vt;
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assert(vs.size() == 8 && "expects 8 vectors");
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assert(llvm::all_of(ValueRange{vs}.getTypes(),
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[&](Type t) { return t == vt; }) &&
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"expects all types to be vector<8xf32>");
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Value t0 = mm256UnpackLoPs(ib, vs[0], vs[1]);
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Value t1 = mm256UnpackHiPs(ib, vs[0], vs[1]);
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Value t2 = mm256UnpackLoPs(ib, vs[2], vs[3]);
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Value t3 = mm256UnpackHiPs(ib, vs[2], vs[3]);
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Value t4 = mm256UnpackLoPs(ib, vs[4], vs[5]);
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Value t5 = mm256UnpackHiPs(ib, vs[4], vs[5]);
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Value t6 = mm256UnpackLoPs(ib, vs[6], vs[7]);
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Value t7 = mm256UnpackHiPs(ib, vs[6], vs[7]);
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using inline_asm::mm256BlendPsAsm;
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Value sh0 = mm256ShufflePs(ib, t0, t2, MaskHelper::shuffle<1, 0, 3, 2>());
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Value sh2 = mm256ShufflePs(ib, t1, t3, MaskHelper::shuffle<1, 0, 3, 2>());
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Value sh4 = mm256ShufflePs(ib, t4, t6, MaskHelper::shuffle<1, 0, 3, 2>());
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Value sh6 = mm256ShufflePs(ib, t5, t7, MaskHelper::shuffle<1, 0, 3, 2>());
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Value s0 =
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mm256BlendPsAsm(ib, t0, sh0, MaskHelper::blend<0, 0, 1, 1, 0, 0, 1, 1>());
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Value s1 =
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mm256BlendPsAsm(ib, t2, sh0, MaskHelper::blend<1, 1, 0, 0, 1, 1, 0, 0>());
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Value s2 =
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mm256BlendPsAsm(ib, t1, sh2, MaskHelper::blend<0, 0, 1, 1, 0, 0, 1, 1>());
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Value s3 =
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mm256BlendPsAsm(ib, t3, sh2, MaskHelper::blend<1, 1, 0, 0, 1, 1, 0, 0>());
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Value s4 =
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mm256BlendPsAsm(ib, t4, sh4, MaskHelper::blend<0, 0, 1, 1, 0, 0, 1, 1>());
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Value s5 =
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mm256BlendPsAsm(ib, t6, sh4, MaskHelper::blend<1, 1, 0, 0, 1, 1, 0, 0>());
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Value s6 =
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mm256BlendPsAsm(ib, t5, sh6, MaskHelper::blend<0, 0, 1, 1, 0, 0, 1, 1>());
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Value s7 =
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mm256BlendPsAsm(ib, t7, sh6, MaskHelper::blend<1, 1, 0, 0, 1, 1, 0, 0>());
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vs[0] = mm256Permute2f128Ps(ib, s0, s4, MaskHelper::permute<2, 0>());
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vs[1] = mm256Permute2f128Ps(ib, s1, s5, MaskHelper::permute<2, 0>());
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vs[2] = mm256Permute2f128Ps(ib, s2, s6, MaskHelper::permute<2, 0>());
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vs[3] = mm256Permute2f128Ps(ib, s3, s7, MaskHelper::permute<2, 0>());
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vs[4] = mm256Permute2f128Ps(ib, s0, s4, MaskHelper::permute<3, 1>());
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vs[5] = mm256Permute2f128Ps(ib, s1, s5, MaskHelper::permute<3, 1>());
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vs[6] = mm256Permute2f128Ps(ib, s2, s6, MaskHelper::permute<3, 1>());
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vs[7] = mm256Permute2f128Ps(ib, s3, s7, MaskHelper::permute<3, 1>());
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}
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/// Rewrite AVX2-specific vector.transpose, for the supported cases and
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/// depending on the `TransposeLoweringOptions`. The lowering supports 2-D
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/// transpose cases and n-D cases that have been decomposed into 2-D
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/// transposition slices. For example, a 3-D transpose:
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///
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/// %0 = vector.transpose %arg0, [2, 0, 1]
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/// : vector<1024x2048x4096xf32> to vector<4096x1024x2048xf32>
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///
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/// could be sliced into 2-D transposes by tiling two of its dimensions to one
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/// of the vector lengths supported by the AVX2 patterns (e.g., 4x8):
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///
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/// %0 = vector.transpose %arg0, [2, 0, 1]
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/// : vector<1x4x8xf32> to vector<8x1x4xf32>
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///
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/// This lowering will analyze the n-D vector.transpose and determine if it's a
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/// supported 2-D transposition slice where any of the AVX2 patterns can be
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/// applied.
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class TransposeOpLowering : public OpRewritePattern<vector::TransposeOp> {
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public:
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using OpRewritePattern<vector::TransposeOp>::OpRewritePattern;
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TransposeOpLowering(LoweringOptions loweringOptions, MLIRContext *context,
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int benefit)
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: OpRewritePattern<vector::TransposeOp>(context, benefit),
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loweringOptions(loweringOptions) {}
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LogicalResult matchAndRewrite(vector::TransposeOp op,
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PatternRewriter &rewriter) const override {
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auto loc = op.getLoc();
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// Check if the source vector type is supported. AVX2 patterns can only be
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// applied to f32 vector types with two dimensions greater than one.
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VectorType srcType = op.getSourceVectorType();
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if (!srcType.getElementType().isF32())
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return rewriter.notifyMatchFailure(op, "Unsupported vector element type");
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auto srcGtOneDims = mlir::vector::isTranspose2DSlice(op);
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if (failed(srcGtOneDims))
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return rewriter.notifyMatchFailure(
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op, "expected transposition on a 2D slice");
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// Retrieve the sizes of the two dimensions greater than one to be
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// transposed.
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int64_t m = srcType.getDimSize(std::get<0>(srcGtOneDims.value()));
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int64_t n = srcType.getDimSize(std::get<1>(srcGtOneDims.value()));
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auto applyRewrite = [&]() {
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ImplicitLocOpBuilder ib(loc, rewriter);
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SmallVector<Value> vs;
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// Reshape the n-D input vector with only two dimensions greater than one
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// to a 2-D vector.
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auto flattenedType =
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VectorType::get({n * m}, op.getSourceVectorType().getElementType());
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auto reshInputType = VectorType::get({m, n}, srcType.getElementType());
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auto reshInput =
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ib.create<vector::ShapeCastOp>(flattenedType, op.getVector());
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reshInput = ib.create<vector::ShapeCastOp>(reshInputType, reshInput);
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// Extract 1-D vectors from the higher-order dimension of the input
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// vector.
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for (int64_t i = 0; i < m; ++i)
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vs.push_back(ib.create<vector::ExtractOp>(reshInput, i));
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// Transpose set of 1-D vectors.
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if (m == 4)
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transpose4x8xf32(ib, vs);
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if (m == 8)
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transpose8x8xf32(ib, vs);
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// Insert transposed 1-D vectors into the higher-order dimension of the
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// output vector.
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Value res = ib.create<arith::ConstantOp>(reshInputType,
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ib.getZeroAttr(reshInputType));
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for (int64_t i = 0; i < m; ++i)
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res = ib.create<vector::InsertOp>(vs[i], res, i);
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// The output vector still has the shape of the input vector (e.g., 4x8).
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// We have to transpose their dimensions and retrieve its original rank
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// (e.g., 1x8x1x4x1).
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res = ib.create<vector::ShapeCastOp>(flattenedType, res);
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res = ib.create<vector::ShapeCastOp>(op.getResultVectorType(), res);
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rewriter.replaceOp(op, res);
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return success();
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};
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if (loweringOptions.transposeOptions.lower4x8xf32_ && m == 4 && n == 8)
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return applyRewrite();
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if (loweringOptions.transposeOptions.lower8x8xf32_ && m == 8 && n == 8)
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return applyRewrite();
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return failure();
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}
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private:
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LoweringOptions loweringOptions;
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};
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void mlir::x86vector::avx2::populateSpecializedTransposeLoweringPatterns(
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RewritePatternSet &patterns, LoweringOptions options, int benefit) {
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patterns.add<TransposeOpLowering>(options, patterns.getContext(), benefit);
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}
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