099fd018d1
0-d vectors are supported now and so these patterns are no longer required. This covers a part of this issue https://github.com/llvm/llvm-project/issues/112913 . Additionally this removes %arg2 in mlir/test/Conversion/GPUCommon/transfer_write.mlir and renames %arg3 to %arg2 as %arg2 was originally not required.
16 lines
627 B
MLIR
16 lines
627 B
MLIR
// RUN: mlir-opt %s --gpu-to-llvm | FileCheck %s
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// CHECK-LABEL: @warp_extract
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// CHECK-SAME: %[[VEC:[a-zA-Z0-9_]+]]: vector<1xf32>
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// CHECK:%[[BASE:[0-9]+]] = llvm.extractvalue
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// CHECK:%[[PTR:[0-9]+]] = llvm.getelementptr %[[BASE]]
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// CHECK:llvm.store %[[VEC]], %[[PTR]] {alignment = 4 : i64} : vector<1xf32>, !llvm.ptr
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func.func @warp_extract(%arg0: index, %arg1: memref<1024x1024xf32>, %arg2: vector<1xf32>) {
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%c0 = arith.constant 0 : index
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gpu.warp_execute_on_lane_0(%arg0)[32] {
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vector.transfer_write %arg2, %arg1[%c0, %c0] {in_bounds = [true]} : vector<1xf32>, memref<1024x1024xf32>
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}
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return
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}
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