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clang-p2996/llvm/test/CodeGen/RISCV
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Craig Topper 814902a03a [RISCV] Fix XTheadba patterns broken since cfc574a6cd. 
Adding an OperandTransform to CSImm12MulBy4 and CSImm12MulBy8 for
Zba broke these patterns. They should have been changed in the same,
but we lacked sufficient testing.
2024-12-26 21:50:35 -08:00
..
GlobalISel
[RISCV][GISel] Port AddiPair optimization (#120463)
2024-12-20 11:32:27 -08:00
intrinsics
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rvv
[RISCV][CG]Use processShuffleMasks for per-register shuffles
2024-12-23 11:18:10 -05:00
abds-neg.ll
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abds.ll
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abdu-neg.ll
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abdu.ll
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add_sext_shl_constant.ll
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add_shl_constant.ll
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add-before-shl.ll
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add-imm.ll
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addc-adde-sube-subc.ll
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addcarry.ll
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addimm-mulimm.ll
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addrspacecast.ll
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aext-to-sext.ll
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aext.ll
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align-loops.ll
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align.ll
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alloca.ll
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allow-check.ll
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alu8.ll
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alu16.ll
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alu32.ll
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alu64.ll
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analyze-branch.ll
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and-add-lsr.ll
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and-shl.ll
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and.ll
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arith-with-overflow.ll
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atomic-cmpxchg-branch-on-result.ll
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atomic-cmpxchg-flag.ll
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atomic-cmpxchg.ll
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atomic-fence.ll
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atomic-load-store.ll
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
atomic-rmw-discard.ll
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atomic-rmw-sub.ll
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atomic-rmw.ll
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atomic-signext.ll
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atomicrmw-cond-sub-clamp.ll
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atomicrmw-uinc-udec-wrap.ll
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attributes-module-flag.ll
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attributes.ll
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
2024-12-14 00:06:58 +05:30
avgceils.ll
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avgceilu.ll
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avgfloors.ll
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avgflooru.ll
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bf16-promote.ll
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bfloat-arith.ll
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bfloat-br-fcmp.ll
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bfloat-convert.ll
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bfloat-fcmp.ll
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bfloat-frem.ll
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bfloat-imm.ll
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bfloat-isnan.ll
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bfloat-mem.ll
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bfloat-select-fcmp.ll
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bfloat-select-icmp.ll
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bfloat.ll
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bitextract-mac.ll
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bitreverse-shift.ll
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bittest.ll
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blockaddress.ll
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branch_zero.ll
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branch-on-zero.ll
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branch-opt.ll
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branch-opt.mir
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branch-relaxation-rv32.ll
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branch-relaxation-rv64.ll
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branch.ll
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bswap-bitreverse.ll
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bswap-shift.ll
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byval.ll
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callee-saved-fpr32s.ll
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callee-saved-fpr64s.ll
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callee-saved-gprs.ll
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calling-conv-half.ll
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calling-conv-ilp32-ilp32f-common.ll
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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calling-conv-ilp32.ll
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calling-conv-ilp32d.ll
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calling-conv-ilp32e.ll
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calling-conv-ilp32f-ilp32d-common.ll
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calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll
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calling-conv-lp64.ll
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calling-conv-lp64e.ll
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calling-conv-rv32f-ilp32.ll
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calling-conv-rv32f-ilp32e.ll
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calling-conv-sext-zext.ll
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calling-conv-vector-float.ll
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calling-conv-vector-on-stack.ll
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calls.ll
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clear-cache.ll
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cm_mvas_mvsa.ll
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cm_mvas_mvsa.mir
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cmov-branch-opt.ll
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cmp-bool.ll
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codemodel-lowering.ll
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compress-double.ll
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compress-float.ll
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compress-inline-asm.ll
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compress-opt-branch.ll
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compress-opt-select.ll
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compress.ll
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condbinops.ll
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condops.ll
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convert-highly-predictable-select-to-branch.ll
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copy-frameindex.mir
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copyprop.ll
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copysign-casts.ll
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ctlz-cttz-ctpop.ll
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ctz_zero_return_test.ll
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disable-tail-calls.ll
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disjoint.ll
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div_minsize.ll
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div-by-constant.ll
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div-pow2.ll
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div.ll
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double_reduct.ll
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double-arith-strict.ll
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double-arith.ll
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double-bitmanip-dagcombines.ll
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double-br-fcmp.ll
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double-calling-conv.ll
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double-convert-strict.ll
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double-convert.ll
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double-fcmp-strict.ll
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double-fcmp.ll
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double-frem.ll
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double-imm.ll
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double-intrinsics-strict.ll
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double-intrinsics.ll
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double-isnan.ll
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double-maximum-minimum.ll
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double-mem.ll
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double-previous-failure.ll
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double-round-conv-sat.ll
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double-round-conv.ll
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double-select-fcmp.ll
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double-select-icmp.ll
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double-stack-spill-restore.ll
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double-zfa.ll
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dso_local_equivalent.ll
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dwarf-eh.ll
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early-clobber-tied-def-subreg-liveness.ll
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eh-dwarf-cfa.ll
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elf-preemption.ll
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emutls.ll
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exception-pointer-register.ll
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fastcc-bf16.ll
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fastcc-float.ll
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fastcc-half.ll
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fastcc-int.ll
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fastcc-without-f-reg.ll
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features-info.ll
[NFC] [RISCV] Refactor class RISCVExtension (#120040)
2024-12-16 19:53:23 +08:00
fixed-csr.ll
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fixups-diff.ll
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fli-licm.ll
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float-arith-strict.ll
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float-arith.ll
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float-bit-preserving-dagcombines.ll
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float-bitmanip-dagcombines.ll
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float-br-fcmp.ll
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float-convert-strict.ll
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float-convert.ll
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float-fcmp-strict.ll
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float-fcmp.ll
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float-frem.ll
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float-imm.ll
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float-intrinsics-strict.ll
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float-intrinsics.ll
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float-isnan.ll
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float-maximum-minimum.ll
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float-mem.ll
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float-round-conv-sat.ll
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float-round-conv.ll
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float-select-fcmp.ll
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float-select-icmp.ll
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float-select-verify.ll
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float-zfa.ll
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flt-rounds.ll
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fmax-fmin.ll
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fold-addi-loadstore.ll
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fold-binop-into-select-return-constant.ll
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fold-binop-into-select.ll
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forced-atomics.ll
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fp16-promote.ll
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fp128.ll
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fp-fcanonicalize.ll
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fpclamptosat.ll
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fpenv.ll
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frame-info.ll
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frame.ll
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frameaddr-returnaddr.ll
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frm-dependency.ll
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get-register-invalid.ll
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get-register-noreserve.ll
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get-register-reserve.ll
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get-setcc-result-type.ll
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ghccc-nest.ll
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ghccc-rv32.ll
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ghccc-rv64.ll
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ghccc-without-f-reg.ll
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global-merge-minsize-smalldata-nonzero.ll
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global-merge-minsize-smalldata-zero.ll
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global-merge-minsize.ll
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global-merge-offset.ll
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global-merge.ll
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graalcc.ll
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half-arith-strict.ll
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half-arith.ll
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half-bitmanip-dagcombines.ll
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half-br-fcmp.ll
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half-convert-strict.ll
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half-convert.ll
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half-fcmp-strict.ll
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half-fcmp.ll
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half-frem.ll
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half-imm.ll
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half-intrinsics.ll
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half-isnan.ll
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half-maximum-minimum.ll
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half-mem.ll
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half-round-conv-sat.ll
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half-round-conv.ll
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half-select-fcmp.ll
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half-select-icmp.ll
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half-zfa-fli.ll
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half-zfa.ll
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hoist-global-addr-base.ll
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hwasan-check-memaccess.ll
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i32-icmp.ll
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i64-icmp.ll
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iabs.ll
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idiv_large.ll
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imm-cse.ll
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imm.ll
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indirectbr.ll
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init-array.ll
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inline-asm-abi-names.ll
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inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll
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inline-asm-d-constraint-f.ll
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inline-asm-d-modifier-N.ll
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inline-asm-f-abi-names.ll
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inline-asm-f-constraint-f.ll
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inline-asm-f-modifier-N.ll
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inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll
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inline-asm-mem-constraint-2.ll
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inline-asm-mem-constraint.ll
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inline-asm-s-constraint-error.ll
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inline-asm-s-constraint.ll
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inline-asm-v-constraint.ll
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inline-asm-xsfvcp.ll
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inline-asm-zdinx-constraint-r.ll
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inline-asm-zfh-constraint-f.ll
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inline-asm-zfh-modifier-N.ll
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inline-asm-zfinx-constraint-r.ll
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inline-asm-zhinx-constraint-r.ll
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inline-asm.ll
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inline-option-directive.ll
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instruction-count-remark.mir
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interrupt-attr-args-error.ll
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interrupt-attr-callee.ll
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interrupt-attr-invalid.ll
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interrupt-attr-nocall.ll
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interrupt-attr-ret-error.ll
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interrupt-attr.ll
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intrinsic-cttz-elts-vscale.ll
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intrinsic-cttz-elts.ll
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isel-optnone.ll
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jumptable-swguarded.ll
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jumptable.ll
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kcfi-isel-mir.ll
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kcfi-mir.ll
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kcfi-patchable-function-prefix.ll
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kcfi.ll
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lack-of-signed-truncation-check.ll
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large-stack.ll
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legalize-fneg.ll
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libcall-tail-calls.ll
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lit.local.cfg
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live-sp.mir
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llvm.exp10.ll
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llvm.frexp.ll
[SDAG] Allow folding stack slots into sincos/frexp in more cases (#118117)
2024-12-17 10:54:17 +00:00
load-setcc-combine.ll
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local-stack-slot-allocation.ll
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loop-strength-reduce-add-cheaper-than-mul.ll
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loop-strength-reduce-loop-invar.ll
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lpad.ll
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lsr-legaladdimm.ll
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machine-combiner-mir.ll
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machine-combiner-strategies.ll
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machine-combiner.ll
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machine-combiner.mir
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machine-cp.mir
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machine-cse.ll
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machine-outliner-and-machine-copy-propagation.ll
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machine-outliner-call.ll
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machine-outliner-cfi.mir
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machine-outliner-leaf-descendants.ll
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machine-outliner-patchable.ll
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machine-outliner-position.mir
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machine-outliner-throw.ll
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machine-pipeliner.ll
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
machine-sink-load-immediate.ll
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machinelicm-address-pseudos.ll
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machinelicm-constant-phys-reg.ll
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machineoutliner-jumptable.mir
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machineoutliner-pcrel-lo.mir
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machineoutliner-x5.mir
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machineoutliner.mir
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MachineSink-implicit-x0.mir
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macro-fusion-lui-addi.ll
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macro-fusions.mir
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make-compressible-for-store-address.mir
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make-compressible-rv64.mir
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make-compressible-zbc-zhinx.mir
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make-compressible-zbc.mir
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make-compressible-zfinx.mir
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make-compressible.mir
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mem64.ll
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mem.ll
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memcmp-optsize.ll
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memcmp.ll
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memcpy-inline.ll
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memcpy.ll
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memset-inline.ll
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memset-pattern.ll
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min-max.ll
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mir-target-flags.ll
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misched-load-clustering.ll
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misched-mem-clustering.mir
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misched-postra-direction.mir
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miss-sp-restore-eh.ll
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module-elf-flags.ll
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module-target-abi2.ll
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module-target-abi3.ll
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module-target-abi.ll
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mul.ll
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musttail-call.ll
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naked-fn-with-frame-pointer.ll
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narrow-shl-cst.ll
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neg-abs.ll
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nest-register.ll
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nomerge.ll
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nontemporal-scalable.ll
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nontemporal.ll
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O0-pipeline.ll
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O3-pipeline.ll
[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461)
2024-12-17 16:19:35 -05:00
opt-w-instrs.mir
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option-nopic.ll
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option-norelax.ll
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option-norvc.ll
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option-pic.ll
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option-relax-relocation.ll
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option-relax.ll
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option-rvc.ll
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optnone-store-no-combine.ll
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or-is-add.ll
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orc-b-patterns.ll
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out-of-reach-emergency-slot.mir
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overflow-intrinsic-optimizations.ll
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overflow-intrinsics.ll
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patchable-function-entry.ll
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pei-crash.ll
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pic-models.ll
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pr40333.ll
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pr51206.ll
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pr53662.mir
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pr55201.ll
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pr56110.ll
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pr56457.ll
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pr58025.ll
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pr58286.ll
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pr58511.ll
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pr63365.ll
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pr63816.ll
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pr64503.ll
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pr64645.ll
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pr64772.ll
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pr64935.ll
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pr65025.ll
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pr66603.ll
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pr68855.ll
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pr69586.ll
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pr80052.mir
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pr84200.ll
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pr84653_pr85190.ll
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
pr88365.ll
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pr90652.ll
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pr90730.ll
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pr92193.ll
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pr94145.ll
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pr94265.ll
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pr95271.ll
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pr95284.ll
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pr96366.ll
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pr97304.ll
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prefer-w-inst.ll
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prefer-w-inst.mir
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prefetch.ll
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prolog-epilogue.ll
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push-pop-opt-crash.ll
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push-pop-popret.ll
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readcyclecounter.ll
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readsteadycounter.ll
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reduce-unnecessary-extension.ll
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reduction-formation.ll
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redundant-copy-from-tail-duplicate.ll
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regalloc-last-chance-recoloring-failure.ll
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relax-per-target-feature.ll
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rem.ll
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remat.ll
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renamable-copy.mir
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repeated-fp-divisors.ll
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replace-with-veclib-sleef-scalable.ll
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reserved-reg-errors.ll
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reserved-regs.ll
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riscv-codegen-prepare-atp.ll
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riscv-codegenprepare-asm.ll
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riscv-codegenprepare.ll
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riscv-func-target-feature.ll
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riscv-tail-dup-size.ll
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rotl-rotr.ll
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rv32-fuchsia.ll
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rv32-inline-asm-pairs.ll
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rv32e.ll
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rv32i-rv64i-float-double.ll
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rv32i-rv64i-half.ll
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rv32xtheadba.ll
[RISCV] Fix XTheadba patterns broken since cfc574a6cd.
2024-12-26 21:50:35 -08:00
rv32xtheadbb.ll
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rv32xtheadbs.ll
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rv32zba.ll
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rv32zbb-intrinsic.ll
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rv32zbb-zbkb.ll
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rv32zbb.ll
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rv32zbc-intrinsic.ll
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rv32zbc-zbkc-intrinsic.ll
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rv32zbkb-intrinsic.ll
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rv32zbkb.ll
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rv32zbkx-intrinsic.ll
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rv32zbs.ll
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rv32zimop-intrinsic.ll
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rv32zknd-intrinsic-autoupgrade.ll
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rv32zknd-intrinsic.ll
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rv32zkne-intrinsic-autoupgrade.ll
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rv32zkne-intrinsic.ll
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rv32zknh-intrinsic.ll
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rv32zksed-intrinsic-autoupgrade.ll
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rv32zksed-intrinsic.ll
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rv32zksh-intrinsic.ll
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rv64-double-convert-strict.ll
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rv64-double-convert.ll
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rv64-float-convert-strict.ll
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rv64-float-convert.ll
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rv64-half-convert-strict.ll
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rv64-half-convert.ll
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rv64-inline-asm-pairs.ll
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rv64-large-stack.ll
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rv64-patchpoint.ll
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rv64-stackmap-args.ll
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rv64-stackmap-frame-setup.ll
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rv64-stackmap-nops.ll
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rv64-stackmap.ll
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rv64-statepoint-call-lowering-x1.ll
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rv64-statepoint-call-lowering-x2.ll
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rv64-statepoint-call-lowering.ll
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rv64-trampoline.ll
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rv64-typepromotion.ll
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rv64d-double-convert-strict.ll
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rv64d-double-convert.ll
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rv64e.ll
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rv64f-float-convert-strict.ll
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rv64f-float-convert.ll
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rv64i-complex-float.ll
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rv64i-demanded-bits.ll
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rv64i-double-softfloat.ll
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rv64i-exhaustive-w-insts.ll
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rv64i-shift-sext.ll
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rv64i-single-softfloat.ll
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rv64i-tricky-shifts.ll
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rv64i-w-insts-legalization.ll
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rv64m-exhaustive-w-insts.ll
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rv64m-w-insts-legalization.ll
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rv64xtheadba.ll
[RISCV] Fix XTheadba patterns broken since cfc574a6cd.
2024-12-26 21:50:35 -08:00
rv64xtheadbb.ll
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rv64xtheadbs.ll
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rv64zba.ll
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rv64zbb-intrinsic.ll
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rv64zbb-zbkb.ll
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rv64zbb.ll
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rv64zbc-intrinsic.ll
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rv64zbc-zbkc-intrinsic.ll
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rv64zbkb-intrinsic.ll
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rv64zbkb.ll
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rv64zbkx-intrinsic.ll
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rv64zbs.ll
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rv64zfh-half-convert-strict.ll
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rv64zfh-half-convert.ll
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rv64zfh-half-intrinsics.ll
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rv64zfhmin-half-convert-strict.ll
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rv64zfhmin-half-convert.ll
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rv64zfhmin-half-intrinsics.ll
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rv64zimop-intrinsic.ll
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rv64zknd-intrinsic.ll
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rv64zknd-zkne-intrinsic.ll
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rv64zkne-intrinsic.ll
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rv64zknh-intrinsic-autoupgrade.ll
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rv64zknh-intrinsic.ll
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rv64zksed-intrinsic-autoupgrade2.ll
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rv64zksed-intrinsic-autoupgrade.ll
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rv64zksed-intrinsic.ll
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rv64zksh-intrinsic-autoupgrade.ll
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rv64zksh-intrinsic.ll
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sadd_sat_plus.ll
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sadd_sat.ll
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saverestore-scs.ll
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saverestore.ll
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scmp.ll
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sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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sdata-sections.ll
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sdiv-pow2-cmov.ll
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select-and.ll
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select-bare.ll
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select-binop-identity.ll
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select-cc.ll
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select-const.ll
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select-constant-xor.ll
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select-optimize-multiple.ll
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select-optimize-multiple.mir
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select-or.ll
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select-to-and-zext.ll
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select.ll
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selectcc-to-shiftand.ll
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setcc-logic.ll
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sext-zext-trunc.ll
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sextw-removal-debug.mir
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sextw-removal.ll
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shadowcallstack.ll
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shift-amount-mod.ll
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shift-and.ll
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shift-masked-shamt.ll
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shifts.ll
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shl-cttz.ll
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shl-demanded.ll
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shlimm-addimm.ll
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short-forward-branch-opt.ll
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shrinkwrap-jump-table.ll
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shrinkwrap.ll
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sifive7-enable-intervals.mir
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signbit-test.ll
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signed-truncation-check.ll
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sink-and-fold-crash.mir
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sink-icmp.ll
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spill-fill-fold.ll
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spill-fpr-scalar.ll
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spir-kernel-cc.ll
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split-offsets.ll
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split-sp-adjust.ll
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split-store.ll
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split-udiv-by-constant.ll
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split-urem-by-constant.ll
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srem-lkk.ll
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srem-seteq-illegal-types.ll
[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461)
2024-12-17 16:19:35 -05:00
srem-vector-lkk.ll
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srodata.ll
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ssub_sat_plus.ll
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ssub_sat.ll
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stack-clash-prologue-nounwind.ll
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stack-clash-prologue.ll
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stack-folding.ll
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stack-guard-global.ll
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stack-guard-tls.ll
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stack-inst-compress.mir
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stack-offset.ll
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stack-protector-target.ll
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stack-realignment-with-variable-sized-objects.ll
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stack-realignment.ll
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stack-slot-coloring.mir
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stack-slot-size.ll
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stack-store-check.ll
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subtarget-features-std-ext.ll
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switch-width.ll
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tagged-globals.ll
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tail-calls.ll
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target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll
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tlsdesc-symbol.ll
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trunc-free.ll
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trunc-nsw-nuw.ll
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typepromotion-overflow.ll
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uadd_sat_plus.ll
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uadd_sat.ll
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ucmp.ll
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umulo-128-legalisation-lowering.ll
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unaligned-load-store.ll
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unfold-masked-merge-scalar-variablemask.ll
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unroll-loop-cse.ll
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urem-lkk.ll
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urem-seteq-illegal-types.ll
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urem-vector-lkk.ll
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usub_sat_plus.ll
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usub_sat.ll
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vararg-ilp32e.ll
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vararg.ll
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varargs-with-fp-and-second-adj.ll
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vector-abi.ll
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vector-tuple-zeroinitializer.ll
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verify-instr.mir
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vlenb.ll
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vscale-demanded-bits.ll
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wide-mem.ll
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wide-scalar-shift-by-byte-multiple-legalization.ll
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wide-scalar-shift-legalization.ll
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xaluo.ll
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xcvalu.ll
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xcvbi.ll
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xcvbitmanip.ll
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xcvmac.ll
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xcvmem.ll
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xray-attribute-instrumentation.ll
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xtheadfmemidx.ll
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xtheadmac.ll
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xtheadmemidx.ll
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xtheadmempair.ll
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zbb-cmp-combine.ll
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zbb-logic-neg-imm.ll
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
zcb-regalloc-hints.ll
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zcmp-additional-stack.ll
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zcmp-cm-popretz.mir
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zcmp-cm-push-pop.mir
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zcmp-prolog-epilog-crash.mir
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zcmp-with-float.ll
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zdinx-asm-constraint.ll
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zdinx-boundary-check.ll
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zdinx-large-spill.mir
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zext-with-load-is-free.ll
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zfh-half-intrinsics-strict.ll
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zfh-half-intrinsics.ll
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zfhmin-half-intrinsics-strict.ll
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zfhmin-half-intrinsics.ll
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zfhmin-imm.ll
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zicfilp-indirect-branch.ll
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zmmul.ll
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