Simon Pilgrim 9237d88001 [X86] isVectorShiftByScalarCheap - don't limit fast XOP vector shifts to 128-bit vectors ...

XOP targets have fast per-element vector shifts and we're better off splitting to 128-bit shifts where necessary (which is what we already do in LowerShift).

2020-05-09 22:24:08 +01:00

..

AArch64

Recommit "[PatternMatch] Match XOR variant of unsigned-add overflow check."

2020-02-23 18:33:18 +00:00

AMDGPU

AMDGPU: Don't assert on unknown address spaces

2020-05-08 12:57:27 -04:00

ARM

[ARM] Replace arm vendor with none. NFC

2020-04-22 18:19:35 +01:00

Mips

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NVPTX

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PowerPC

[CodeGen] Fix the computation of the alignment of split stores.

2020-02-12 10:37:30 +01:00

SPARC

[TargetLower] Update shouldFormOverflowOp check if math is used.

2020-02-19 11:28:33 +01:00

X86

[X86] isVectorShiftByScalarCheap - don't limit fast XOP vector shifts to 128-bit vectors

2020-05-09 22:24:08 +01:00

dom-tree.ll

[CodeGenPrepare][test] Add REQUIRES to two tests after D73754

2020-02-02 09:53:17 -08:00

sink-shift-and-trunc.ll

[CodeGenPrepare] Fix use-after-free

2019-08-16 23:10:34 +00:00

skip-merging-case-block.ll

[CodeGenPrepare][test] Add REQUIRES to two tests after D73754

2020-02-02 09:53:17 -08:00