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clang-p2996/llvm/lib/Target/RISCV
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Jim Lin 9d6064ec49 Revert "[RISCV] Make CanLowerReturn protected for downstream maintenance" 
This reverts commit d775841d7d.
2020-05-12 18:49:17 +08:00
..
AsmParser
[RISCV] Update debug scratch register names
2020-05-05 08:46:07 -07:00
Disassembler
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
MCTargetDesc
[RISCV] Remove unused forward declarations. NFC.
2020-04-23 16:30:45 +01:00
TargetInfo
…
Utils
[RISCV] Update debug scratch register names
2020-05-05 08:46:07 -07:00
CMakeLists.txt
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LLVMBuild.txt
…
RISCV.h
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RISCV.td
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
RISCVAsmPrinter.cpp
[RISCV] ELF attribute section for RISC-V.
2020-03-31 16:16:19 +08:00
RISCVCallingConv.td
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVExpandPseudoInsts.cpp
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RISCVFrameLowering.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
RISCVFrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
RISCVInstrFormats.td
…
RISCVInstrFormatsC.td
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RISCVInstrInfo.cpp
[MachineOutliner] Teach outliner to set live-ins
2020-04-22 14:19:26 -07:00
RISCVInstrInfo.h
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RISCVInstrInfo.td
[RISCV] Add instruction definition for dret
2020-04-24 13:27:43 -07:00
RISCVInstrInfoA.td
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RISCVInstrInfoB.td
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
RISCVInstrInfoC.td
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RISCVInstrInfoD.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoF.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoM.td
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RISCVInstructionSelector.cpp
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RISCVISelDAGToDAG.cpp
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
RISCVISelDAGToDAG.h
[RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp
2020-04-01 11:30:21 +08:00
RISCVISelLowering.cpp
[SelectionDAG] Use Align/MaybeAlign for ConstantPoolSDNode.
2020-05-08 16:04:11 -07:00
RISCVISelLowering.h
Revert "[RISCV] Make CanLowerReturn protected for downstream maintenance"
2020-05-12 18:49:17 +08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td
…
RISCVSchedRocket32.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedRocket64.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedule.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVSubtarget.h
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
RISCVSystemOperands.td
[RISCV] Update debug scratch register names
2020-05-05 08:46:07 -07:00
RISCVTargetMachine.cpp
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RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile
2020-03-20 21:57:34 -07:00
RISCVTargetObjectFile.h
[RISCV] Remove unused forward declarations. NFC.
2020-04-23 16:30:45 +01:00
RISCVTargetTransformInfo.cpp
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00
RISCVTargetTransformInfo.h
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00