365c405411
This introduce basic tablegen infra such as CSKY{InstrFormats,InstrInfo,RegisterInfo,}.td.
For now, only add instruction definitions for basic CSKY ISA operations, and the instruction format and register info are almost complete.
Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later.
Differential Revision: https://reviews.llvm.org/D89180
33 lines
1.2 KiB
TableGen
33 lines
1.2 KiB
TableGen
//===-- CSKY.td - Describe the CSKY Target Machine ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Registers, calling conventions, instruction descriptions.
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//===----------------------------------------------------------------------===//
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include "CSKYRegisterInfo.td"
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include "CSKYInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// CSKY processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic-csky", NoSchedModel, []>;
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//===----------------------------------------------------------------------===//
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// Define the CSKY target.
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//===----------------------------------------------------------------------===//
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def CSKYInstrInfo : InstrInfo;
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def CSKY : Target {
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let InstructionSet = CSKYInstrInfo;
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}
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