Files
clang-p2996/llvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir
Joe Nash 314e29ed2b [AMDGPU] Add _e64 suffix to VOP3 Insts
Previously, instructions which could be
expressed as VOP3 in addition to another
encoding had a _e64 suffix on the tablegen
record name, while those
only available as VOP3 did not. With this
patch, all VOP3s will have the _e64 suffix.
The assembly does not change, only  the mir.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D94341

Change-Id: Ia8ec8890d47f8f94bbbdac43745b4e9dd2b03423
2021-01-12 18:33:18 -05:00

25 lines
953 B
YAML

# RUN: llc -march=amdgcn -mcpu=gfx908 -start-before=si-pre-emit-peephole %s -o - | FileCheck -check-prefix=GCN %s
# Verify that the dedicated hazard recognizer pass is run after late peephole
# optimizations. New hazards can be introduced if instructions are removed by
# passes that are run before the final hazard recognizer.
---
# GCN-LABEL: {{^}}mai_hazard_pass_ordering_optimize_vcc_branch:
# GCN: v_accvgpr_read_b32
# GCN-NEXT: s_nop
# GCN-NEXT: flat_load_dword
name: mai_hazard_pass_ordering_optimize_vcc_branch
body: |
bb.0:
$vgpr0 = V_MOV_B32_e32 1, implicit $exec
$vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec
$sgpr8_sgpr9 = S_MOV_B64 -1
$vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vcc = S_ANDN2_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
bb.1:
S_ENDPGM 0
...