4b80647367
This is a (last big?) part of the patch series to make SimplifyCFG
preserve DomTree. Currently, it still does not actually preserve it,
even thought it is pretty much fully updated to preserve it.
Once the default is flipped, a valid DomTree must be passed into
simplifyCFG, which means that whatever pass calls simplifyCFG,
should also be smart about DomTree's.
As far as i can see from `check-llvm` with default flipped,
this is the last LLVM test batch (other than bugpoint tests)
that needed fixes to not break with default flipped.
The changes here are boringly identical to the ones i did
over 42+ times/commits recently already,
so while AMDGPU is outside of my normal ecosystem,
i'm going to go for post-commit review here,
like in all the other 42+ changes.
Note that while the pass is taught to preserve {,Post}DomTree,
it still doesn't do that by default, because simplifycfg
still doesn't do that by default, and flipping default
in this pass will implicitly flip the default for simplifycfg.
That will happen, but not right now.
130 lines
5.9 KiB
LLVM
130 lines
5.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
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; This should end with an no-op sequence of exec mask manipulations
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; Mask should be in original state after executed unreachable block
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; GCN-LABEL: {{^}}uniform_br_trivial_ret_divergent_br_trivial_unreachable:
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; GCN: s_cbranch_scc1 [[RET_BB:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: ; %else
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; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN: ; %bb.{{[0-9]+}}: ; %unreachable.bb
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; GCN-NEXT: ; divergent unreachable
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; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %Flow
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; GCN-NEXT: s_or_b64 exec, exec
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; GCN-NEXT: [[RET_BB]]:
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; GCN-NEXT: ; return
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; GCN-NEXT: .Lfunc_end0
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define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_trivial_ret_divergent_br_trivial_unreachable([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <8 x i32>] addrspace(4)* inreg %arg2, i32 addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, i32 inreg %arg17, i32 %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {
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entry:
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%i.i = extractelement <2 x i32> %arg7, i32 0
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%j.i = extractelement <2 x i32> %arg7, i32 1
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%i.f.i = bitcast i32 %i.i to float
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%j.f.i = bitcast i32 %j.i to float
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%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #2
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%p2 = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
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%p87 = fmul float %p2, %p2
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%p88 = fadd float %p87, %p87
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%p93 = fadd float %p88, %p88
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%p97 = fmul float %p93, %p93
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%p102 = fsub float %p97, %p97
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%p104 = fmul float %p102, %p102
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%p106 = fadd float 0.000000e+00, %p104
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%p108 = fadd float %p106, %p106
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%uniform.cond = icmp slt i32 %arg17, 0
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br i1 %uniform.cond, label %ret.bb, label %else
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else: ; preds = %main_body
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%p124 = fmul float %p108, %p108
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%p125 = fsub float %p124, %p124
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%divergent.cond = fcmp olt float %p125, 0.000000e+00
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br i1 %divergent.cond, label %ret.bb, label %unreachable.bb
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unreachable.bb: ; preds = %else
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unreachable
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ret.bb: ; preds = %else, %main_body
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ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef
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}
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; GCN-LABEL: {{^}}uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable:
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; GCN: s_cbranch_vccz
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; GCN: ; %bb.{{[0-9]+}}: ; %Flow
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; GCN: s_cbranch_execnz [[RETURN:BB[0-9]+_[0-9]+]]
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; GCN: ; %UnifiedReturnBlock
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; GCN-NEXT: s_or_b64 exec, exec
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; GCN-NEXT: s_waitcnt
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; GCN: BB{{[0-9]+_[0-9]+}}: ; %else
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; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN-NEXT: ; %unreachable.bb
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; GCN: ds_write_b32
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; GCN: ; divergent unreachable
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; GCN: ; %ret.bb
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; GCN: store_dword
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define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable([9 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [17 x <8 x i32>] addrspace(4)* inreg %arg2, i32 addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 inreg %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {
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main_body:
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%i.i = extractelement <2 x i32> %arg7, i32 0
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%j.i = extractelement <2 x i32> %arg7, i32 1
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%i.f.i = bitcast i32 %i.i to float
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%j.f.i = bitcast i32 %j.i to float
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%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #2
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%p2 = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
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%p87 = fmul float %p2, %p2
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%p88 = fadd float %p87, %p87
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%p93 = fadd float %p88, %p88
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%p97 = fmul float %p93, %p93
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%p102 = fsub float %p97, %p97
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%p104 = fmul float %p102, %p102
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%p106 = fadd float 0.000000e+00, %p104
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%p108 = fadd float %p106, %p106
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%uniform.cond = icmp slt i32 %arg18, 0
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br i1 %uniform.cond, label %ret.bb, label %else
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else: ; preds = %main_body
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%p124 = fmul float %p108, %p108
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%p125 = fsub float %p124, %p124
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%divergent.cond = fcmp olt float %p125, 0.000000e+00
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br i1 %divergent.cond, label %ret.bb, label %unreachable.bb
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unreachable.bb: ; preds = %else
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store volatile i32 8, i32 addrspace(3)* undef
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unreachable
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ret.bb: ; preds = %else, %main_body
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store volatile i32 11, i32 addrspace(1)* undef
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ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.fabs.f32(float) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.sqrt.f32(float) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.floor.f32(float) #1
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attributes #0 = { "InitialPSInputAddr"="36983" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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