f333736757
These VGPRs should be reserved and therefore do not need "correct" liveness. They should not have undef uses, which can still cause issues.
105 lines
4.9 KiB
YAML
105 lines
4.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
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# Make sure spill/restore of 192 bit registers works. We have to
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# settle for a MIR test for now since inlineasm fails without 192-bit
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# MVT.
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---
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name: spill_restore_sgpr192
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_sgpr192
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; SPILLED: bb.0:
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; SPILLED: successors: %bb.1(0x80000000)
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; SPILLED: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; SPILLED: SI_SPILL_S192_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, %stack.0, implicit $exec, implicit $sgpr32 :: (store 24 into %stack.0, align 4, addrspace 5)
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; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED: bb.1:
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; SPILLED: successors: %bb.2(0x80000000)
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; SPILLED: S_NOP 1
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; SPILLED: bb.2:
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; SPILLED: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 = SI_SPILL_S192_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load 24 from %stack.0, align 4, addrspace 5)
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; SPILLED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED-LABEL: name: spill_restore_sgpr192
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; EXPANDED: bb.0:
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; EXPANDED: successors: %bb.1(0x80000000)
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; EXPANDED: liveins: $vgpr0
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; EXPANDED: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, $vgpr0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr6, 2, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr7, 3, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr8, 4, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: $vgpr0 = V_WRITELANE_B32 killed $sgpr9, 5, $vgpr0, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED: bb.1:
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; EXPANDED: successors: %bb.2(0x80000000)
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; EXPANDED: liveins: $vgpr0
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; EXPANDED: S_NOP 1
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; EXPANDED: bb.2:
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; EXPANDED: liveins: $vgpr0
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; EXPANDED: $sgpr4 = V_READLANE_B32 $vgpr0, 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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; EXPANDED: $sgpr5 = V_READLANE_B32 $vgpr0, 1
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; EXPANDED: $sgpr6 = V_READLANE_B32 $vgpr0, 2
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; EXPANDED: $sgpr7 = V_READLANE_B32 $vgpr0, 3
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; EXPANDED: $sgpr8 = V_READLANE_B32 $vgpr0, 4
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; EXPANDED: $sgpr9 = V_READLANE_B32 $vgpr0, 5
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; EXPANDED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
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bb.0:
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S_NOP 0, implicit-def %0:sgpr_192
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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---
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name: spill_restore_vgpr192
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_vgpr192
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; SPILLED: bb.0:
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; SPILLED: successors: %bb.1(0x80000000)
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; SPILLED: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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; SPILLED: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store 24 into %stack.0, align 4, addrspace 5)
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; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED: bb.1:
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; SPILLED: successors: %bb.2(0x80000000)
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; SPILLED: S_NOP 1
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; SPILLED: bb.2:
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; SPILLED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 24 from %stack.0, align 4, addrspace 5)
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; SPILLED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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; EXPANDED-LABEL: name: spill_restore_vgpr192
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; EXPANDED: bb.0:
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; EXPANDED: successors: %bb.1(0x80000000)
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; EXPANDED: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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; EXPANDED: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store 24 into %stack.0, align 4, addrspace 5)
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; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED: bb.1:
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; EXPANDED: successors: %bb.2(0x80000000)
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; EXPANDED: S_NOP 1
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; EXPANDED: bb.2:
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; EXPANDED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 24 from %stack.0, align 4, addrspace 5)
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; EXPANDED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
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bb.0:
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S_NOP 0, implicit-def %0:vreg_192
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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