16fb1c7aae
This improves our coverage of these operations and shows that we use really large constants for division by constant on i8/i16 especially on RV64. The issue is that BuildSDIV/BuildUDIV are limited to legal types so we have to promote to i64 before it kicks in. At that point we've lost the range information for the original type.
336 lines
9.5 KiB
LLVM
336 lines
9.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IM %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IM %s
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define i32 @urem(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: urem:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __umodsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: urem:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: remu a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: urem:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: srli a1, a1, 32
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: urem:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: remuw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i32 %a, %b
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ret i32 %1
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}
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define i32 @srem(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: srem:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __modsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: srem:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: rem a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: srem:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: call __moddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: srem:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: remw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i32 %a, %b
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ret i32 %1
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}
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define i64 @urem64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: urem64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __umoddi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: urem64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IM-NEXT: call __umoddi3@plt
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; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: urem64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: urem64:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: remu a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i64 %a, %b
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ret i64 %1
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}
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define i64 @srem64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: srem64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __moddi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: srem64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi sp, sp, -16
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; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IM-NEXT: call __moddi3@plt
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; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: srem64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __moddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: srem64:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: rem a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i64 %a, %b
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ret i64 %1
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}
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define i8 @urem8(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: urem8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: andi a1, a1, 255
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; RV32I-NEXT: call __umodsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: urem8:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: andi a1, a1, 255
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; RV32IM-NEXT: andi a0, a0, 255
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; RV32IM-NEXT: remu a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: urem8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: andi a1, a1, 255
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: urem8:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: andi a1, a1, 255
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; RV64IM-NEXT: andi a0, a0, 255
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; RV64IM-NEXT: remuw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i8 %a, %b
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ret i8 %1
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}
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define i8 @srem8(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: srem8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 24
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; RV32I-NEXT: slli a1, a1, 24
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; RV32I-NEXT: srai a1, a1, 24
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; RV32I-NEXT: call __modsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: srem8:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: slli a1, a1, 24
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; RV32IM-NEXT: srai a1, a1, 24
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; RV32IM-NEXT: slli a0, a0, 24
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; RV32IM-NEXT: srai a0, a0, 24
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; RV32IM-NEXT: rem a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: srem8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: srai a0, a0, 56
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srai a1, a1, 56
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; RV64I-NEXT: call __moddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: srem8:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a1, a1, 56
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; RV64IM-NEXT: srai a1, a1, 56
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; RV64IM-NEXT: slli a0, a0, 56
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; RV64IM-NEXT: srai a0, a0, 56
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; RV64IM-NEXT: rem a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i8 %a, %b
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ret i8 %1
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}
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define i16 @urem16(i16 %a, i16 %b) nounwind {
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; RV32I-LABEL: urem16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: lui a2, 16
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; RV32I-NEXT: addi a2, a2, -1
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: and a1, a1, a2
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; RV32I-NEXT: call __umodsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: urem16:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: lui a2, 16
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; RV32IM-NEXT: addi a2, a2, -1
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; RV32IM-NEXT: and a1, a1, a2
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; RV32IM-NEXT: and a0, a0, a2
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; RV32IM-NEXT: remu a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: urem16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: lui a2, 16
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; RV64I-NEXT: addiw a2, a2, -1
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: call __umoddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: urem16:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: lui a2, 16
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; RV64IM-NEXT: addiw a2, a2, -1
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; RV64IM-NEXT: and a1, a1, a2
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; RV64IM-NEXT: and a0, a0, a2
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; RV64IM-NEXT: remuw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = urem i16 %a, %b
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ret i16 %1
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}
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define i16 @srem16(i16 %a, i16 %b) nounwind {
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; RV32I-LABEL: srem16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: slli a0, a0, 16
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; RV32I-NEXT: srai a0, a0, 16
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; RV32I-NEXT: slli a1, a1, 16
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; RV32I-NEXT: srai a1, a1, 16
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; RV32I-NEXT: call __modsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: srem16:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: slli a1, a1, 16
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; RV32IM-NEXT: srai a1, a1, 16
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; RV32IM-NEXT: slli a0, a0, 16
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; RV32IM-NEXT: srai a0, a0, 16
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; RV32IM-NEXT: rem a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: srem16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srai a0, a0, 48
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; RV64I-NEXT: slli a1, a1, 48
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; RV64I-NEXT: srai a1, a1, 48
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; RV64I-NEXT: call __moddi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: srem16:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a1, a1, 48
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; RV64IM-NEXT: srai a1, a1, 48
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; RV64IM-NEXT: slli a0, a0, 48
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; RV64IM-NEXT: srai a0, a0, 48
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; RV64IM-NEXT: rem a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i16 %a, %b
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ret i16 %1
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}
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