22e839f4b2
immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. This recommits r300932 and r300930, which was causing dag-combine to loop forever. The problem was that optimizeLogicalImm was returning true even when there was no change to the immediate node (which happened when the immediate was all zeros or ones), which caused dag-combine to push and pop the same node to the work list over and over again without making any progress. This commit fixes the bug by returning false early in optimizeLogicalImm if the immediate is all zeros or ones. Also, it changes the code to compare the immediate with 0 or Mask rather than calling countPopulation. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 301019
65 lines
1.2 KiB
LLVM
65 lines
1.2 KiB
LLVM
; RUN: llc -o - %s -mtriple=aarch64-- | FileCheck %s
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; CHECK-LABEL: and1:
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; CHECK: and {{w[0-9]+}}, w0, #0xfffffffd
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define void @and1(i32 %a, i8* nocapture %p) {
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entry:
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%and = and i32 %a, 253
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%conv = trunc i32 %and to i8
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store i8 %conv, i8* %p, align 1
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ret void
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}
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; (a & 0x3dfd) | 0xffffc000
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;
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; CHECK-LABEL: and2:
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; CHECK: and {{w[0-9]+}}, w0, #0xfdfdfdfd
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define i32 @and2(i32 %a) {
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entry:
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%and = and i32 %a, 15869
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%or = or i32 %and, -16384
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ret i32 %or
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}
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; (a & 0x19) | 0xffffffc0
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;
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; CHECK-LABEL: and3:
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; CHECK: and {{w[0-9]+}}, w0, #0x99999999
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define i32 @and3(i32 %a) {
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entry:
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%and = and i32 %a, 25
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%or = or i32 %and, -64
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ret i32 %or
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}
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; (a & 0xc5600) | 0xfff1f1ff
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;
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; CHECK-LABEL: and4:
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; CHECK: and {{w[0-9]+}}, w0, #0xfffc07ff
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define i32 @and4(i32 %a) {
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entry:
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%and = and i32 %a, 787968
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%or = or i32 %and, -921089
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ret i32 %or
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}
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; Make sure we don't shrink or optimize an XOR's immediate operand if the
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; immediate is -1. Instruction selection turns (and ((xor $mask, -1), $v0)) into
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; a BIC.
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; CHECK-LABEL: xor1:
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; CHECK: orr [[R0:w[0-9]+]], wzr, #0x38
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; CHECK: bic {{w[0-9]+}}, [[R0]], w0, lsl #3
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define i32 @xor1(i32 %a) {
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entry:
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%shl = shl i32 %a, 3
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%xor = and i32 %shl, 56
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%and = xor i32 %xor, 56
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ret i32 %and
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}
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