f53865daa4
We have to widen the operands to 32 bits and then we can either use hardware division if it is available or lower to a libcall otherwise. At the moment it is not enough to set the Legalizer action to WidenScalar, since for libcalls it won't know what to do (it won't be able to find what size to widen to, because it will find Libcall and not Legal for 32 bits). To hack around this limitation, we request Custom lowering, and as part of that we widen first and then we run another legalizeInstrStep on the widened DIV. llvm-svn: 301166
69 lines
2.0 KiB
LLVM
69 lines
2.0 KiB
LLVM
; We use V6 ops so we can easily check for the extensions (sxth vs bit tricks).
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; RUN: llc -mtriple arm-gnueabi -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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; RUN: llc -mtriple arm-gnueabi -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
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; RUN: llc -mtriple arm-gnu -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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; RUN: llc -mtriple arm-gnu -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
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define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: test_sdiv_i32:
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; HWDIV: sdiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_idiv
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; SOFT-DEFAULT: blx __divsi3
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%r = sdiv i32 %a, %b
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ret i32 %r
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}
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define arm_aapcscc i32 @test_udiv_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: test_udiv_i32:
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; HWDIV: udiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_uidiv
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; SOFT-DEFAULT: blx __udivsi3
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%r = udiv i32 %a, %b
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ret i32 %r
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}
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define arm_aapcscc i16 @test_sdiv_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: test_sdiv_i16:
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; CHECK-DAG: sxth r0, r0
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; CHECK-DAG: sxth r1, r1
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; HWDIV: sdiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_idiv
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; SOFT-DEFAULT: blx __divsi3
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%r = sdiv i16 %a, %b
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ret i16 %r
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}
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define arm_aapcscc i16 @test_udiv_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: test_udiv_i16:
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; CHECK-DAG: uxth r0, r0
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; CHECK-DAG: uxth r1, r1
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; HWDIV: udiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_uidiv
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; SOFT-DEFAULT: blx __udivsi3
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%r = udiv i16 %a, %b
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ret i16 %r
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}
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define arm_aapcscc i8 @test_sdiv_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: test_sdiv_i8:
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; CHECK-DAG: sxtb r0, r0
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; CHECK-DAG: sxtb r1, r1
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; HWDIV: sdiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_idiv
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; SOFT-DEFAULT: blx __divsi3
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%r = sdiv i8 %a, %b
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ret i8 %r
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}
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define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: test_udiv_i8:
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; CHECK-DAG: uxtb r0, r0
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; CHECK-DAG: uxtb r1, r1
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; HWDIV: udiv r0, r0, r1
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; SOFT-AEABI: blx __aeabi_uidiv
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; SOFT-DEFAULT: blx __udivsi3
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%r = udiv i8 %a, %b
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ret i8 %r
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}
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