fe5f4c397f
Pass no longer handles skips. Pass now removes unnecessary unconditional branches and lowers early termination branches. Hence rename to SILateBranchLowering. Move code to handle returns to epilog from SIPreEmitPeephole into SILateBranchLowering. This means SIPreEmitPeephole only contains optional optimisations, and all required transforms are in SILateBranchLowering. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D98915
88 lines
2.9 KiB
LLVM
88 lines
2.9 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope %s
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; Although it's modeled without any control flow in order to get better code
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; out of the structurizer, @llvm.amdgcn.kill actually ends the thread that calls
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; it with "true". In case it's called in a provably infinite loop, we still
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; need to successfully exit and export something, even if we can't know where
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; to jump to in the LLVM IR. Therefore we insert a null export ourselves in
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; this case right before the s_endpgm to avoid GPU hangs, which is what this
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; tests.
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; CHECK-LABEL: return_void
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; Make sure that we remove the done bit from the original export
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; CHECK: exp mrt0 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} vm
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; CHECK: exp null off, off, off, off done vm
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @return_void(float %0) #0 {
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main_body:
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%cmp = fcmp olt float %0, 1.000000e+01
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br i1 %cmp, label %end, label %loop
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loop:
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call void @llvm.amdgcn.kill(i1 false) #3
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br label %loop
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end:
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 0., float 0., float 0., float 1., i1 true, i1 true) #3
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ret void
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}
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; Check that we also remove the done bit from compressed exports correctly.
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; CHECK-LABEL: return_void_compr
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; CHECK: exp mrt0 v{{[0-9]+}}, off, v{{[0-9]+}}, off compr vm
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; CHECK: exp null off, off, off, off done vm
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @return_void_compr(float %0) #0 {
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main_body:
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%cmp = fcmp olt float %0, 1.000000e+01
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br i1 %cmp, label %end, label %loop
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loop:
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call void @llvm.amdgcn.kill(i1 false) #3
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br label %loop
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end:
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 5, <2 x i16> < i16 0, i16 0 >, <2 x i16> < i16 0, i16 0 >, i1 true, i1 true) #3
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ret void
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}
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; test the case where there's only a kill in an infinite loop
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; CHECK-LABEL: only_kill
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; CHECK: exp null off, off, off, off done vm
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; CHECK-NEXT: s_endpgm
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; SILateBranchLowering inserts an extra null export here, but it should be harmless.
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; CHECK: exp null off, off, off, off done vm
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @only_kill() #0 {
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main_body:
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br label %loop
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loop:
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call void @llvm.amdgcn.kill(i1 false) #3
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br label %loop
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}
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; Check that the epilog is the final block
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; CHECK-LABEL: return_nonvoid
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; CHECK: exp null off, off, off, off done vm
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB{{[0-9]+}}_{{[0-9]+}}:
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define amdgpu_ps float @return_nonvoid(float %0) #0 {
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main_body:
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%cmp = fcmp olt float %0, 1.000000e+01
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br i1 %cmp, label %end, label %loop
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loop:
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call void @llvm.amdgcn.kill(i1 false) #3
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br label %loop
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end:
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ret float 0.
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}
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declare void @llvm.amdgcn.kill(i1) #0
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #0
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declare void @llvm.amdgcn.exp.compr.v2i16(i32 immarg, i32 immarg, <2 x i16>, <2 x i16>, i1 immarg, i1 immarg) #0
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attributes #0 = { nounwind }
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