quic_hchandel 950d281eb2 [RISCV] Add ISel patterns for Qualcomm uC Xqcicm extension (#145643) ...

Add codegen patterns for the conditional move instructions in this
extension

2025-06-27 12:25:48 +05:30

..

AArch64

[AArch64] Use 0-cycle reg2reg MOVs for FPR32, FPR16, FPR8 (#144152)

2025-06-26 19:40:20 +03:00

AMDGPU

[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)

2025-06-26 14:08:13 -07:00

ARC

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ARM

[IfConversion] Fix bug related to !HasFallThrough (#145471)

2025-06-25 09:30:26 +02:00

AVR

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BPF

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CSKY

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DirectX

[DirectX] Limit GEP transformations to Arrays (#145758)

2025-06-25 17:17:52 -04:00

Generic

[RemoveDIs] Fix rotten --implicit-check-not lines (#144711)

2025-06-24 12:32:50 +01:00

Hexagon

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Inputs

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Lanai

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LoongArch

[LoongArch] Pre-commit tests for optimizing insert extracted fp elements

2025-06-27 11:19:06 +08:00

M68k

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Mips

[MIPS][MSA] compare_float.ll - regenerate checks

2025-06-25 11:38:01 +01:00

MIR

[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)

2025-06-24 11:09:36 +02:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Allow directly storing immediates to improve readability (#145552)

2025-06-25 18:46:39 -07:00

PowerPC

[PowerPC] eliminate RLWINM instruction following LBARX as possible (#144089)

2025-06-25 09:26:40 -04:00

RISCV

[RISCV] Add ISel patterns for Qualcomm uC Xqcicm extension (#145643)

2025-06-27 12:25:48 +05:30

SPARC

CodeGen: Emit error if getRegisterByName fails (#145194)

2025-06-23 16:33:35 +09:00

SPIRV

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SystemZ

[GOFF] Add writing of text records (#137235)

2025-06-26 13:50:40 -04:00

Thumb

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Thumb2

[DAG] Fold nested add(add(reduce(a), b), add(reduce(c), d)) (#115150)

2025-06-24 13:08:59 +01:00

VE

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WebAssembly

[WebAssembly] Enable a limited amount of stackification for debug code (#136510)

2025-06-24 11:40:47 -07:00

WinCFGuard

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WinEH

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X86

[X86] abds-vector-128.ll - regenerate VPTERNLOG asm comment

2025-06-26 18:54:27 +01:00

XCore

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Xtensa

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