9cfeba5b12
This is rework of; - D30046 (LLT) Since I have introduced `llvm-min-tblgen` as D146352, `llvm-tblgen` may depend on `CodeGen`. `LowLevlType.h` originally belonged to `CodeGen`. Almost all userse are still under `CodeGen` or `Target`. I think `CodeGen` is the right place to put `LowLevelType.h`. `MachineValueType.h` may be moved as well. (later, D149024) I have made many modules depend on `CodeGen`. It is consistent but inefficient. It will be split out later, D148769 Besides, I had to isolate MVT and LLT in modmap, since `llvm::PredicateInfo` clashes between `TableGen/CodeGenSchedule.h` and `Transforms/Utils/PredicateInfo.h`. (I think better to introduce namespace llvm::TableGen) Depends on D145937, D146352, and D148768. Differential Revision: https://reviews.llvm.org/D148767
75 lines
2.6 KiB
C++
75 lines
2.6 KiB
C++
//===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUGlobalISelUtils.h"
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#include "GCNSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/IR/Constants.h"
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using namespace llvm;
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using namespace MIPatternMatch;
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std::pair<Register, unsigned>
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AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
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GISelKnownBits *KnownBits) {
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MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
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if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
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unsigned Offset;
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const MachineOperand &Op = Def->getOperand(1);
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if (Op.isImm())
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Offset = Op.getImm();
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else
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Offset = Op.getCImm()->getZExtValue();
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return std::pair(Register(), Offset);
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}
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int64_t Offset;
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if (Def->getOpcode() == TargetOpcode::G_ADD) {
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// TODO: Handle G_OR used for add case
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if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
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return std::pair(Def->getOperand(1).getReg(), Offset);
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// FIXME: matcher should ignore copies
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if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
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return std::pair(Def->getOperand(1).getReg(), Offset);
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}
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Register Base;
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if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
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KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
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return std::pair(Base, Offset);
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// Handle G_PTRTOINT (G_PTR_ADD base, const) case
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if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
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MachineInstr *Base;
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if (mi_match(Def->getOperand(1).getReg(), MRI,
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m_GPtrAdd(m_MInstr(Base), m_ICst(Offset)))) {
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// If Base was int converted to pointer, simply return int and offset.
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if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
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return std::pair(Base->getOperand(1).getReg(), Offset);
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// Register returned here will be of pointer type.
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return std::pair(Base->getOperand(0).getReg(), Offset);
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}
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}
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return std::pair(Reg, 0);
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}
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bool AMDGPU::hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget,
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const LLT &Ty) {
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if (Ty == LLT::scalar(32))
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return Subtarget.hasAtomicFaddRtnInsts();
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if (Ty == LLT::fixed_vector(2, 16) || Ty == LLT::scalar(64))
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return Subtarget.hasGFX90AInsts();
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return false;
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}
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