cfe9a134bb
Names '64BitDPP' and especially 'DPP64' were found misleading, and DPP64 can easily be mixed with DPP16 and DPP8 while these are different concepts. DPP16 and DPP8 refers to lanes where DPP64 refers to the operand size. In fact the essential part here is that these instructions are executed on the DP ALU, so rename the feature accordingly. I have also found a bug in a check for these instructions, which is fixed here and a common utility function is now used. Differential Revision: https://reviews.llvm.org/D158465
1358 lines
43 KiB
C++
1358 lines
43 KiB
C++
//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#include "SIDefines.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Alignment.h"
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#include <array>
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#include <functional>
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#include <utility>
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struct amd_kernel_code_t;
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namespace llvm {
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struct Align;
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class Argument;
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class Function;
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class GlobalValue;
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class MCInstrInfo;
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class MCRegisterClass;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class StringRef;
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class Triple;
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class raw_ostream;
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namespace amdhsa {
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struct kernel_descriptor_t;
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}
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namespace AMDGPU {
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struct IsaVersion;
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enum {
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AMDHSA_COV2 = 2,
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AMDHSA_COV3 = 3,
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AMDHSA_COV4 = 4,
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AMDHSA_COV5 = 5
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};
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/// \returns HSA OS ABI Version identification.
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std::optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
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/// \returns True if HSA OS ABI Version identification is 2,
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/// false otherwise.
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bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
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/// \returns True if HSA OS ABI Version identification is 3,
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/// false otherwise.
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bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
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/// \returns True if HSA OS ABI Version identification is 4,
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/// false otherwise.
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bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
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/// \returns True if HSA OS ABI Version identification is 5,
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/// false otherwise.
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bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
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/// \returns True if HSA OS ABI Version identification is 3 and above,
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/// false otherwise.
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bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
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/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
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unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
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/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
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unsigned getHostcallImplicitArgPosition(unsigned COV);
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unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
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unsigned getCompletionActionImplicitArgPosition(unsigned COV);
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/// \returns Code object version.
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unsigned getAmdhsaCodeObjectVersion();
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/// \returns Code object version.
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unsigned getCodeObjectVersion(const Module &M);
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struct GcnBufferFormatInfo {
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unsigned Format;
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unsigned BitsPerComp;
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unsigned NumComponents;
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unsigned NumFormat;
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unsigned DataFormat;
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};
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struct MAIInstInfo {
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uint16_t Opcode;
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bool is_dgemm;
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bool is_gfx940_xdl;
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};
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#define GET_MIMGBaseOpcode_DECL
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#define GET_MIMGDim_DECL
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#define GET_MIMGEncoding_DECL
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#define GET_MIMGLZMapping_DECL
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#define GET_MIMGMIPMapping_DECL
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#define GET_MIMGBiASMapping_DECL
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#define GET_MAIInstInfoTable_DECL
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#include "AMDGPUGenSearchableTables.inc"
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namespace IsaInfo {
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enum {
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// The closed Vulkan driver sets 96, which limits the wave count to 8 but
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// doesn't spill SGPRs as much as when 80 is set.
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FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
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TRAP_NUM_SGPRS = 16
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};
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enum class TargetIDSetting {
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Unsupported,
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Any,
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Off,
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On
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};
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class AMDGPUTargetID {
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private:
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const MCSubtargetInfo &STI;
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TargetIDSetting XnackSetting;
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TargetIDSetting SramEccSetting;
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unsigned CodeObjectVersion;
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public:
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explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
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~AMDGPUTargetID() = default;
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/// \return True if the current xnack setting is not "Unsupported".
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bool isXnackSupported() const {
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return XnackSetting != TargetIDSetting::Unsupported;
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}
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/// \returns True if the current xnack setting is "On" or "Any".
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bool isXnackOnOrAny() const {
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return XnackSetting == TargetIDSetting::On ||
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XnackSetting == TargetIDSetting::Any;
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}
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/// \returns True if current xnack setting is "On" or "Off",
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/// false otherwise.
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bool isXnackOnOrOff() const {
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return getXnackSetting() == TargetIDSetting::On ||
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getXnackSetting() == TargetIDSetting::Off;
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}
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/// \returns The current xnack TargetIDSetting, possible options are
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/// "Unsupported", "Any", "Off", and "On".
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TargetIDSetting getXnackSetting() const {
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return XnackSetting;
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}
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void setCodeObjectVersion(unsigned COV) {
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CodeObjectVersion = COV;
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}
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/// Sets xnack setting to \p NewXnackSetting.
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void setXnackSetting(TargetIDSetting NewXnackSetting) {
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XnackSetting = NewXnackSetting;
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}
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/// \return True if the current sramecc setting is not "Unsupported".
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bool isSramEccSupported() const {
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return SramEccSetting != TargetIDSetting::Unsupported;
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}
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/// \returns True if the current sramecc setting is "On" or "Any".
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bool isSramEccOnOrAny() const {
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return SramEccSetting == TargetIDSetting::On ||
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SramEccSetting == TargetIDSetting::Any;
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}
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/// \returns True if current sramecc setting is "On" or "Off",
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/// false otherwise.
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bool isSramEccOnOrOff() const {
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return getSramEccSetting() == TargetIDSetting::On ||
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getSramEccSetting() == TargetIDSetting::Off;
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}
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/// \returns The current sramecc TargetIDSetting, possible options are
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/// "Unsupported", "Any", "Off", and "On".
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TargetIDSetting getSramEccSetting() const {
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return SramEccSetting;
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}
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/// Sets sramecc setting to \p NewSramEccSetting.
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void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
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SramEccSetting = NewSramEccSetting;
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}
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void setTargetIDFromFeaturesString(StringRef FS);
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void setTargetIDFromTargetIDStream(StringRef TargetID);
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/// \returns String representation of an object.
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std::string toString() const;
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};
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/// \returns Wavefront size for given subtarget \p STI.
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unsigned getWavefrontSize(const MCSubtargetInfo *STI);
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/// \returns Local memory size in bytes for given subtarget \p STI.
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unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
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/// \returns Maximum addressable local memory size in bytes for given subtarget
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/// \p STI.
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unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI);
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/// \returns Number of execution units per compute unit for given subtarget \p
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/// STI.
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unsigned getEUsPerCU(const MCSubtargetInfo *STI);
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/// \returns Maximum number of work groups per compute unit for given subtarget
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/// \p STI and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum number of waves per execution unit for given subtarget \p
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/// STI.
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unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
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/// \returns Maximum number of waves per execution unit for given subtarget \p
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/// STI without any kind of limitation.
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unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
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/// \returns Number of waves per execution unit required to support the given \p
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/// FlatWorkGroupSize.
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unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum flat work group size for given subtarget \p STI.
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unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
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/// \returns Maximum flat work group size for given subtarget \p STI.
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unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
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/// \returns Number of waves per work group for given subtarget \p STI and
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/// \p FlatWorkGroupSize.
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unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize);
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/// \returns SGPR allocation granularity for given subtarget \p STI.
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unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
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/// \returns SGPR encoding granularity for given subtarget \p STI.
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unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
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/// \returns Total number of SGPRs for given subtarget \p STI.
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unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
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/// \returns Addressable number of SGPRs for given subtarget \p STI.
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unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
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/// \returns Minimum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
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/// \returns Maximum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
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bool Addressable);
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/// \returns Number of extra SGPRs implicitly required by given subtarget \p
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/// STI when the given special registers are used.
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
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bool FlatScrUsed, bool XNACKUsed);
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/// \returns Number of extra SGPRs implicitly required by given subtarget \p
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/// STI when the given special registers are used. XNACK is inferred from
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/// \p STI.
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
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bool FlatScrUsed);
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/// \returns Number of SGPR blocks needed for given subtarget \p STI when
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/// \p NumSGPRs are used. \p NumSGPRs should already include any special
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/// register counts.
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unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
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/// \returns VGPR allocation granularity for given subtarget \p STI.
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///
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/// For subtargets which support it, \p EnableWavefrontSize32 should match
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/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
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unsigned
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getVGPRAllocGranule(const MCSubtargetInfo *STI,
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std::optional<bool> EnableWavefrontSize32 = std::nullopt);
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/// \returns VGPR encoding granularity for given subtarget \p STI.
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///
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/// For subtargets which support it, \p EnableWavefrontSize32 should match
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/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
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unsigned getVGPREncodingGranule(
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const MCSubtargetInfo *STI,
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std::optional<bool> EnableWavefrontSize32 = std::nullopt);
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/// \returns Total number of VGPRs for given subtarget \p STI.
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unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
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/// \returns Addressable number of VGPRs for given subtarget \p STI.
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unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
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/// \returns Minimum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
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/// \returns Maximum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p STI.
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unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
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/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
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/// subtarget \p STI.
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unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,
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unsigned NumVGPRs);
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/// \returns Number of VGPR blocks needed for given subtarget \p STI when
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/// \p NumVGPRs are used.
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///
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/// For subtargets which support it, \p EnableWavefrontSize32 should match the
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/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
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unsigned
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getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
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std::optional<bool> EnableWavefrontSize32 = std::nullopt);
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} // end namespace IsaInfo
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LLVM_READONLY
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
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LLVM_READONLY
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inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
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return getNamedOperandIdx(Opcode, NamedIdx) != -1;
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}
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LLVM_READONLY
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int getSOPPWithRelaxation(uint16_t Opcode);
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struct MIMGBaseOpcodeInfo {
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MIMGBaseOpcode BaseOpcode;
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bool Store;
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bool Atomic;
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bool AtomicX2;
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bool Sampler;
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bool Gather4;
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uint8_t NumExtraArgs;
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bool Gradients;
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bool G16;
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bool Coordinates;
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bool LodOrClampOrMip;
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bool HasD16;
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bool MSAA;
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bool BVH;
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bool A16;
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};
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LLVM_READONLY
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const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
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LLVM_READONLY
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const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
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struct MIMGDimInfo {
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MIMGDim Dim;
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uint8_t NumCoords;
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uint8_t NumGradients;
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bool MSAA;
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bool DA;
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uint8_t Encoding;
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const char *AsmSuffix;
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};
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LLVM_READONLY
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const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
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LLVM_READONLY
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const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
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LLVM_READONLY
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const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
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struct MIMGLZMappingInfo {
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MIMGBaseOpcode L;
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MIMGBaseOpcode LZ;
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};
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struct MIMGMIPMappingInfo {
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MIMGBaseOpcode MIP;
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MIMGBaseOpcode NONMIP;
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};
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struct MIMGBiasMappingInfo {
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MIMGBaseOpcode Bias;
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MIMGBaseOpcode NoBias;
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};
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struct MIMGOffsetMappingInfo {
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MIMGBaseOpcode Offset;
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MIMGBaseOpcode NoOffset;
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};
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struct MIMGG16MappingInfo {
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MIMGBaseOpcode G;
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MIMGBaseOpcode G16;
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};
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LLVM_READONLY
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const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
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struct WMMAOpcodeMappingInfo {
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unsigned Opcode2Addr;
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unsigned Opcode3Addr;
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};
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LLVM_READONLY
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|
const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
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|
|
|
LLVM_READONLY
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|
const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
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|
LLVM_READONLY
|
|
const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
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|
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|
LLVM_READONLY
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|
const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
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|
|
LLVM_READONLY
|
|
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
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unsigned VDataDwords, unsigned VAddrDwords);
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|
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LLVM_READONLY
|
|
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
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|
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|
LLVM_READONLY
|
|
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
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|
const MIMGDimInfo *Dim, bool IsA16,
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|
bool IsG16Supported);
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|
|
struct MIMGInfo {
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uint16_t Opcode;
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uint16_t BaseOpcode;
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uint8_t MIMGEncoding;
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uint8_t VDataDwords;
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uint8_t VAddrDwords;
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uint8_t VAddrOperands;
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};
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|
|
|
LLVM_READONLY
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|
const MIMGInfo *getMIMGInfo(unsigned Opc);
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|
|
|
LLVM_READONLY
|
|
int getMTBUFBaseOpcode(unsigned Opc);
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|
|
|
LLVM_READONLY
|
|
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
|
|
|
|
LLVM_READONLY
|
|
int getMTBUFElements(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getMTBUFHasVAddr(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getMTBUFHasSrsrc(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getMTBUFHasSoffset(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
int getMUBUFBaseOpcode(unsigned Opc);
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|
|
|
LLVM_READONLY
|
|
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
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|
LLVM_READONLY
|
|
int getMUBUFElements(unsigned Opc);
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|
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|
LLVM_READONLY
|
|
bool getMUBUFHasVAddr(unsigned Opc);
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|
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LLVM_READONLY
|
|
bool getMUBUFHasSrsrc(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getMUBUFHasSoffset(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getMUBUFIsBufferInv(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getSMEMIsBuffer(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getVOP1IsSingle(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getVOP2IsSingle(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getVOP3IsSingle(unsigned Opc);
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|
|
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LLVM_READONLY
|
|
bool isVOPC64DPP(unsigned Opc);
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|
|
|
/// Returns true if MAI operation is a double precision GEMM.
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|
LLVM_READONLY
|
|
bool getMAIIsDGEMM(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
bool getMAIIsGFX940XDL(unsigned Opc);
|
|
|
|
struct CanBeVOPD {
|
|
bool X;
|
|
bool Y;
|
|
};
|
|
|
|
LLVM_READONLY
|
|
CanBeVOPD getCanBeVOPD(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
|
|
uint8_t NumComponents,
|
|
uint8_t NumFormat,
|
|
const MCSubtargetInfo &STI);
|
|
LLVM_READONLY
|
|
const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
|
|
const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READONLY
|
|
int getMCOpcode(uint16_t Opcode, unsigned Gen);
|
|
|
|
LLVM_READONLY
|
|
unsigned getVOPDOpcode(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
int getVOPDFull(unsigned OpX, unsigned OpY);
|
|
|
|
LLVM_READONLY
|
|
bool isVOPD(unsigned Opc);
|
|
|
|
LLVM_READNONE
|
|
bool isMAC(unsigned Opc);
|
|
|
|
LLVM_READNONE
|
|
bool isPermlane16(unsigned Opc);
|
|
|
|
LLVM_READNONE
|
|
bool isGenericAtomic(unsigned Opc);
|
|
|
|
namespace VOPD {
|
|
|
|
enum Component : unsigned {
|
|
DST = 0,
|
|
SRC0,
|
|
SRC1,
|
|
SRC2,
|
|
|
|
DST_NUM = 1,
|
|
MAX_SRC_NUM = 3,
|
|
MAX_OPR_NUM = DST_NUM + MAX_SRC_NUM
|
|
};
|
|
|
|
// LSB mask for VGPR banks per VOPD component operand.
|
|
// 4 banks result in a mask 3, setting 2 lower bits.
|
|
constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
|
|
|
|
enum ComponentIndex : unsigned { X = 0, Y = 1 };
|
|
constexpr unsigned COMPONENTS[] = {ComponentIndex::X, ComponentIndex::Y};
|
|
constexpr unsigned COMPONENTS_NUM = 2;
|
|
|
|
// Properties of VOPD components.
|
|
class ComponentProps {
|
|
private:
|
|
unsigned SrcOperandsNum = 0;
|
|
unsigned MandatoryLiteralIdx = ~0u;
|
|
bool HasSrc2Acc = false;
|
|
|
|
public:
|
|
ComponentProps() = default;
|
|
ComponentProps(const MCInstrDesc &OpDesc);
|
|
|
|
// Return the total number of src operands this component has.
|
|
unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
|
|
|
|
// Return the number of src operands of this component visible to the parser.
|
|
unsigned getCompParsedSrcOperandsNum() const {
|
|
return SrcOperandsNum - HasSrc2Acc;
|
|
}
|
|
|
|
// Return true iif this component has a mandatory literal.
|
|
bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
|
|
|
|
// If this component has a mandatory literal, return component operand
|
|
// index of this literal (i.e. either Component::SRC1 or Component::SRC2).
|
|
unsigned getMandatoryLiteralCompOperandIndex() const {
|
|
assert(hasMandatoryLiteral());
|
|
return MandatoryLiteralIdx;
|
|
}
|
|
|
|
// Return true iif this component has operand
|
|
// with component index CompSrcIdx and this operand may be a register.
|
|
bool hasRegSrcOperand(unsigned CompSrcIdx) const {
|
|
assert(CompSrcIdx < Component::MAX_SRC_NUM);
|
|
return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
|
|
}
|
|
|
|
// Return true iif this component has tied src2.
|
|
bool hasSrc2Acc() const { return HasSrc2Acc; }
|
|
|
|
private:
|
|
bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
|
|
assert(CompSrcIdx < Component::MAX_SRC_NUM);
|
|
return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
|
|
}
|
|
};
|
|
|
|
enum ComponentKind : unsigned {
|
|
SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
|
|
COMPONENT_X, // A VOPD instruction, X component.
|
|
COMPONENT_Y, // A VOPD instruction, Y component.
|
|
MAX = COMPONENT_Y
|
|
};
|
|
|
|
// Interface functions of this class map VOPD component operand indices
|
|
// to indices of operands in MachineInstr/MCInst or parsed operands array.
|
|
//
|
|
// Note that this class operates with 3 kinds of indices:
|
|
// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
|
|
// - MC operand indices (they refer operands in a MachineInstr/MCInst);
|
|
// - parsed operand indices (they refer operands in parsed operands array).
|
|
//
|
|
// For SINGLE components mapping between these indices is trivial.
|
|
// But things get more complicated for COMPONENT_X and
|
|
// COMPONENT_Y because these components share the same
|
|
// MachineInstr/MCInst and the same parsed operands array.
|
|
// Below is an example of component operand to parsed operand
|
|
// mapping for the following instruction:
|
|
//
|
|
// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
|
|
//
|
|
// PARSED COMPONENT PARSED
|
|
// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
|
|
// -------------------------------------------------------------------
|
|
// "v_dual_add_f32" 0
|
|
// v_dual_add_f32 v255 0 (DST) --> 1
|
|
// v4 1 (SRC0) --> 2
|
|
// v5 2 (SRC1) --> 3
|
|
// "::" 4
|
|
// "v_dual_mov_b32" 5
|
|
// v_dual_mov_b32 v6 0 (DST) --> 6
|
|
// v1 1 (SRC0) --> 7
|
|
// -------------------------------------------------------------------
|
|
//
|
|
class ComponentLayout {
|
|
private:
|
|
// Regular MachineInstr/MCInst operands are ordered as follows:
|
|
// dst, src0 [, other src operands]
|
|
// VOPD MachineInstr/MCInst operands are ordered as follows:
|
|
// dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
|
|
// Each ComponentKind has operand indices defined below.
|
|
static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
|
|
static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
|
|
|
|
// Parsed operands of regular instructions are ordered as follows:
|
|
// Mnemo dst src0 [vsrc1 ...]
|
|
// Parsed VOPD operands are ordered as follows:
|
|
// OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
|
|
// OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
|
|
// Each ComponentKind has operand indices defined below.
|
|
static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
|
|
4 /* + OpX.ParsedSrcNum */};
|
|
static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
|
|
2, 2, 5 /* + OpX.ParsedSrcNum */};
|
|
|
|
private:
|
|
const ComponentKind Kind;
|
|
const ComponentProps PrevComp;
|
|
|
|
public:
|
|
// Create layout for COMPONENT_X or SINGLE component.
|
|
ComponentLayout(ComponentKind Kind) : Kind(Kind) {
|
|
assert(Kind == ComponentKind::SINGLE || Kind == ComponentKind::COMPONENT_X);
|
|
}
|
|
|
|
// Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
|
|
ComponentLayout(const ComponentProps &OpXProps)
|
|
: Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
|
|
|
|
public:
|
|
// Return the index of dst operand in MCInst operands.
|
|
unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
|
|
|
|
// Return the index of the specified src operand in MCInst operands.
|
|
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
|
|
assert(CompSrcIdx < Component::MAX_SRC_NUM);
|
|
return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
|
|
}
|
|
|
|
// Return the index of dst operand in the parsed operands array.
|
|
unsigned getIndexOfDstInParsedOperands() const {
|
|
return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
|
|
}
|
|
|
|
// Return the index of the specified src operand in the parsed operands array.
|
|
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
|
|
assert(CompSrcIdx < Component::MAX_SRC_NUM);
|
|
return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
|
|
}
|
|
|
|
private:
|
|
unsigned getPrevCompSrcNum() const {
|
|
return PrevComp.getCompSrcOperandsNum();
|
|
}
|
|
unsigned getPrevCompParsedSrcNum() const {
|
|
return PrevComp.getCompParsedSrcOperandsNum();
|
|
}
|
|
};
|
|
|
|
// Layout and properties of VOPD components.
|
|
class ComponentInfo : public ComponentLayout, public ComponentProps {
|
|
public:
|
|
// Create ComponentInfo for COMPONENT_X or SINGLE component.
|
|
ComponentInfo(const MCInstrDesc &OpDesc,
|
|
ComponentKind Kind = ComponentKind::SINGLE)
|
|
: ComponentLayout(Kind), ComponentProps(OpDesc) {}
|
|
|
|
// Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
|
|
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
|
|
: ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
|
|
|
|
// Map component operand index to parsed operand index.
|
|
// Return 0 if the specified operand does not exist.
|
|
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
|
|
};
|
|
|
|
// Properties of VOPD instructions.
|
|
class InstInfo {
|
|
private:
|
|
const ComponentInfo CompInfo[COMPONENTS_NUM];
|
|
|
|
public:
|
|
using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
|
|
|
|
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
|
|
: CompInfo{OpX, OpY} {}
|
|
|
|
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
|
|
: CompInfo{OprInfoX, OprInfoY} {}
|
|
|
|
const ComponentInfo &operator[](size_t ComponentIdx) const {
|
|
assert(ComponentIdx < COMPONENTS_NUM);
|
|
return CompInfo[ComponentIdx];
|
|
}
|
|
|
|
// Check VOPD operands constraints.
|
|
// GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
|
|
// for the specified component and MC operand. The callback must return 0
|
|
// if the operand is not a register or not a VGPR.
|
|
bool hasInvalidOperand(
|
|
std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
|
|
return getInvalidCompOperandIndex(GetRegIdx).has_value();
|
|
}
|
|
|
|
// Check VOPD operands constraints.
|
|
// Return the index of an invalid component operand, if any.
|
|
std::optional<unsigned> getInvalidCompOperandIndex(
|
|
std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
|
|
|
|
private:
|
|
RegIndices
|
|
getRegIndices(unsigned ComponentIdx,
|
|
std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
|
|
};
|
|
|
|
} // namespace VOPD
|
|
|
|
LLVM_READONLY
|
|
std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
|
|
|
|
LLVM_READONLY
|
|
// Get properties of 2 single VOP1/VOP2 instructions
|
|
// used as components to create a VOPD instruction.
|
|
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
|
|
|
|
LLVM_READONLY
|
|
// Get properties of VOPD X and Y components.
|
|
VOPD::InstInfo
|
|
getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
|
|
|
|
LLVM_READONLY
|
|
bool isTrue16Inst(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
|
|
|
|
LLVM_READONLY
|
|
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
|
|
|
|
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
|
|
const MCSubtargetInfo *STI);
|
|
|
|
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(
|
|
const MCSubtargetInfo *STI);
|
|
|
|
bool isGroupSegment(const GlobalValue *GV);
|
|
bool isGlobalSegment(const GlobalValue *GV);
|
|
bool isReadOnlySegment(const GlobalValue *GV);
|
|
|
|
/// \returns True if constants should be emitted to .text section for given
|
|
/// target triple \p TT, false otherwise.
|
|
bool shouldEmitConstantsToTextSection(const Triple &TT);
|
|
|
|
/// \returns Integer value requested using \p F's \p Name attribute.
|
|
///
|
|
/// \returns \p Default if attribute is not present.
|
|
///
|
|
/// \returns \p Default and emits error if requested value cannot be converted
|
|
/// to integer.
|
|
int getIntegerAttribute(const Function &F, StringRef Name, int Default);
|
|
|
|
/// \returns A pair of integer values requested using \p F's \p Name attribute
|
|
/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
|
|
/// is false).
|
|
///
|
|
/// \returns \p Default if attribute is not present.
|
|
///
|
|
/// \returns \p Default and emits error if one of the requested values cannot be
|
|
/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
|
|
/// not present.
|
|
std::pair<unsigned, unsigned>
|
|
getIntegerPairAttribute(const Function &F, StringRef Name,
|
|
std::pair<unsigned, unsigned> Default,
|
|
bool OnlyFirstRequired = false);
|
|
|
|
/// Represents the counter values to wait for in an s_waitcnt instruction.
|
|
///
|
|
/// Large values (including the maximum possible integer) can be used to
|
|
/// represent "don't care" waits.
|
|
struct Waitcnt {
|
|
unsigned VmCnt = ~0u;
|
|
unsigned ExpCnt = ~0u;
|
|
unsigned LgkmCnt = ~0u;
|
|
unsigned VsCnt = ~0u;
|
|
|
|
Waitcnt() = default;
|
|
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
|
|
: VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {}
|
|
|
|
static Waitcnt allZero(bool HasVscnt) {
|
|
return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
|
|
}
|
|
static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
|
|
|
|
bool hasWait() const {
|
|
return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
|
|
}
|
|
|
|
bool hasWaitExceptVsCnt() const {
|
|
return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
|
|
}
|
|
|
|
bool hasWaitVsCnt() const {
|
|
return VsCnt != ~0u;
|
|
}
|
|
|
|
Waitcnt combined(const Waitcnt &Other) const {
|
|
return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
|
|
std::min(LgkmCnt, Other.LgkmCnt),
|
|
std::min(VsCnt, Other.VsCnt));
|
|
}
|
|
};
|
|
|
|
/// \returns Vmcnt bit mask for given isa \p Version.
|
|
unsigned getVmcntBitMask(const IsaVersion &Version);
|
|
|
|
/// \returns Expcnt bit mask for given isa \p Version.
|
|
unsigned getExpcntBitMask(const IsaVersion &Version);
|
|
|
|
/// \returns Lgkmcnt bit mask for given isa \p Version.
|
|
unsigned getLgkmcntBitMask(const IsaVersion &Version);
|
|
|
|
/// \returns Waitcnt bit mask for given isa \p Version.
|
|
unsigned getWaitcntBitMask(const IsaVersion &Version);
|
|
|
|
/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
|
|
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
|
|
|
|
/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
|
|
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
|
|
|
|
/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
|
|
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
|
|
|
|
/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
|
|
/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
|
|
/// \p Lgkmcnt respectively.
|
|
///
|
|
/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
|
|
/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
|
|
/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
|
|
/// \p Vmcnt = \p Waitcnt[15:10] (gfx11+)
|
|
/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
|
|
/// \p Expcnt = \p Waitcnt[2:0] (gfx11+)
|
|
/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
|
|
/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
|
|
/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+)
|
|
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
|
|
|
|
Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
|
|
|
|
/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
|
|
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Vmcnt);
|
|
|
|
/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
|
|
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Expcnt);
|
|
|
|
/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
|
|
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Lgkmcnt);
|
|
|
|
/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
|
|
/// \p Version.
|
|
///
|
|
/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
|
|
/// Waitcnt[2:0] = \p Expcnt (gfx11+)
|
|
/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
|
|
/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
|
|
/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
|
|
/// Waitcnt[9:4] = \p Lgkmcnt (gfx11+)
|
|
/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
|
|
/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
|
|
/// Waitcnt[15:10] = \p Vmcnt (gfx11+)
|
|
/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
|
|
///
|
|
/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
|
|
/// isa \p Version.
|
|
unsigned encodeWaitcnt(const IsaVersion &Version,
|
|
unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
|
|
|
|
unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
|
|
|
|
namespace Hwreg {
|
|
|
|
LLVM_READONLY
|
|
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READNONE
|
|
bool isValidHwreg(int64_t Id);
|
|
|
|
LLVM_READNONE
|
|
bool isValidHwregOffset(int64_t Offset);
|
|
|
|
LLVM_READNONE
|
|
bool isValidHwregWidth(int64_t Width);
|
|
|
|
LLVM_READNONE
|
|
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
|
|
|
|
LLVM_READNONE
|
|
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
|
|
|
|
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
|
|
|
|
} // namespace Hwreg
|
|
|
|
namespace DepCtr {
|
|
|
|
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
|
|
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
|
|
const MCSubtargetInfo &STI);
|
|
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
|
|
const MCSubtargetInfo &STI);
|
|
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
|
|
bool &IsDefault, const MCSubtargetInfo &STI);
|
|
|
|
/// \returns Decoded VaVdst from given immediate \p Encoded.
|
|
unsigned decodeFieldVaVdst(unsigned Encoded);
|
|
|
|
/// \returns Decoded VmVsrc from given immediate \p Encoded.
|
|
unsigned decodeFieldVmVsrc(unsigned Encoded);
|
|
|
|
/// \returns Decoded SaSdst from given immediate \p Encoded.
|
|
unsigned decodeFieldSaSdst(unsigned Encoded);
|
|
|
|
/// \returns \p VmVsrc as an encoded Depctr immediate.
|
|
unsigned encodeFieldVmVsrc(unsigned VmVsrc);
|
|
|
|
/// \returns \p Encoded combined with encoded \p VmVsrc.
|
|
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
|
|
|
|
/// \returns \p VaVdst as an encoded Depctr immediate.
|
|
unsigned encodeFieldVaVdst(unsigned VaVdst);
|
|
|
|
/// \returns \p Encoded combined with encoded \p VaVdst.
|
|
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
|
|
|
|
/// \returns \p SaSdst as an encoded Depctr immediate.
|
|
unsigned encodeFieldSaSdst(unsigned SaSdst);
|
|
|
|
/// \returns \p Encoded combined with encoded \p SaSdst.
|
|
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
|
|
|
|
} // namespace DepCtr
|
|
|
|
namespace Exp {
|
|
|
|
bool getTgtName(unsigned Id, StringRef &Name, int &Index);
|
|
|
|
LLVM_READONLY
|
|
unsigned getTgtId(const StringRef Name);
|
|
|
|
LLVM_READNONE
|
|
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
|
|
|
|
} // namespace Exp
|
|
|
|
namespace MTBUFFormat {
|
|
|
|
LLVM_READNONE
|
|
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
|
|
|
|
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
|
|
|
|
int64_t getDfmt(const StringRef Name);
|
|
|
|
StringRef getDfmtName(unsigned Id);
|
|
|
|
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
|
|
|
|
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
|
|
|
|
bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
|
|
|
|
bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
|
|
|
|
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
|
|
|
|
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
|
|
|
|
bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
|
|
|
|
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
|
|
const MCSubtargetInfo &STI);
|
|
|
|
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
|
|
|
|
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
|
|
|
|
} // namespace MTBUFFormat
|
|
|
|
namespace SendMsg {
|
|
|
|
LLVM_READONLY
|
|
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READONLY
|
|
int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
|
|
|
|
LLVM_READNONE
|
|
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READNONE
|
|
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READNONE
|
|
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READNONE
|
|
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
|
|
bool Strict = true);
|
|
|
|
LLVM_READNONE
|
|
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
|
|
const MCSubtargetInfo &STI, bool Strict = true);
|
|
|
|
LLVM_READNONE
|
|
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READNONE
|
|
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
|
|
|
|
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
|
|
uint16_t &StreamId, const MCSubtargetInfo &STI);
|
|
|
|
LLVM_READNONE
|
|
uint64_t encodeMsg(uint64_t MsgId,
|
|
uint64_t OpId,
|
|
uint64_t StreamId);
|
|
|
|
} // namespace SendMsg
|
|
|
|
|
|
unsigned getInitialPSInputAddr(const Function &F);
|
|
|
|
bool getHasColorExport(const Function &F);
|
|
|
|
bool getHasDepthExport(const Function &F);
|
|
|
|
LLVM_READNONE
|
|
bool isShader(CallingConv::ID CC);
|
|
|
|
LLVM_READNONE
|
|
bool isGraphics(CallingConv::ID CC);
|
|
|
|
LLVM_READNONE
|
|
bool isCompute(CallingConv::ID CC);
|
|
|
|
LLVM_READNONE
|
|
bool isEntryFunctionCC(CallingConv::ID CC);
|
|
|
|
// These functions are considered entrypoints into the current module, i.e. they
|
|
// are allowed to be called from outside the current module. This is different
|
|
// from isEntryFunctionCC, which is only true for functions that are entered by
|
|
// the hardware. Module entry points include all entry functions but also
|
|
// include functions that can be called from other functions inside or outside
|
|
// the current module. Module entry functions are allowed to allocate LDS.
|
|
LLVM_READNONE
|
|
bool isModuleEntryFunctionCC(CallingConv::ID CC);
|
|
|
|
LLVM_READNONE
|
|
bool isChainCC(CallingConv::ID CC);
|
|
|
|
bool isKernelCC(const Function *Func);
|
|
|
|
// FIXME: Remove this when calling conventions cleaned up
|
|
LLVM_READNONE
|
|
inline bool isKernel(CallingConv::ID CC) {
|
|
switch (CC) {
|
|
case CallingConv::AMDGPU_KERNEL:
|
|
case CallingConv::SPIR_KERNEL:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool hasXNACK(const MCSubtargetInfo &STI);
|
|
bool hasSRAMECC(const MCSubtargetInfo &STI);
|
|
bool hasMIMG_R128(const MCSubtargetInfo &STI);
|
|
bool hasA16(const MCSubtargetInfo &STI);
|
|
bool hasG16(const MCSubtargetInfo &STI);
|
|
bool hasPackedD16(const MCSubtargetInfo &STI);
|
|
bool hasGDS(const MCSubtargetInfo &STI);
|
|
unsigned getNSAMaxSize(const MCSubtargetInfo &STI);
|
|
|
|
bool isSI(const MCSubtargetInfo &STI);
|
|
bool isCI(const MCSubtargetInfo &STI);
|
|
bool isVI(const MCSubtargetInfo &STI);
|
|
bool isGFX9(const MCSubtargetInfo &STI);
|
|
bool isGFX9_GFX10(const MCSubtargetInfo &STI);
|
|
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
|
|
bool isGFX8Plus(const MCSubtargetInfo &STI);
|
|
bool isGFX9Plus(const MCSubtargetInfo &STI);
|
|
bool isGFX10(const MCSubtargetInfo &STI);
|
|
bool isGFX10Plus(const MCSubtargetInfo &STI);
|
|
bool isNotGFX10Plus(const MCSubtargetInfo &STI);
|
|
bool isGFX10Before1030(const MCSubtargetInfo &STI);
|
|
bool isGFX11(const MCSubtargetInfo &STI);
|
|
bool isGFX11Plus(const MCSubtargetInfo &STI);
|
|
bool isNotGFX11Plus(const MCSubtargetInfo &STI);
|
|
bool isGCN3Encoding(const MCSubtargetInfo &STI);
|
|
bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
|
|
bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
|
|
bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
|
|
bool isGFX90A(const MCSubtargetInfo &STI);
|
|
bool isGFX940(const MCSubtargetInfo &STI);
|
|
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
|
|
bool hasMAIInsts(const MCSubtargetInfo &STI);
|
|
bool hasVOPD(const MCSubtargetInfo &STI);
|
|
int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
|
|
|
|
/// Is Reg - scalar register
|
|
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
|
|
|
|
/// If \p Reg is a pseudo reg, return the correct hardware register given
|
|
/// \p STI otherwise return \p Reg.
|
|
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
|
|
|
|
/// Convert hardware register \p Reg to a pseudo register
|
|
LLVM_READNONE
|
|
unsigned mc2PseudoReg(unsigned Reg);
|
|
|
|
LLVM_READNONE
|
|
bool isInlineValue(unsigned Reg);
|
|
|
|
/// Is this an AMDGPU specific source operand? These include registers,
|
|
/// inline constants, literals and mandatory literals (KImm).
|
|
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// Is this a KImm operand?
|
|
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// Is this floating-point operand?
|
|
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// Does this operand support only inlinable literals?
|
|
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// Get the size in bits of a register from the register class \p RC.
|
|
unsigned getRegBitWidth(unsigned RCID);
|
|
|
|
/// Get the size in bits of a register from the register class \p RC.
|
|
unsigned getRegBitWidth(const MCRegisterClass &RC);
|
|
|
|
/// Get size of register operand
|
|
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
|
|
unsigned OpNo);
|
|
|
|
LLVM_READNONE
|
|
inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
|
|
switch (OpInfo.OperandType) {
|
|
case AMDGPU::OPERAND_REG_IMM_INT32:
|
|
case AMDGPU::OPERAND_REG_IMM_FP32:
|
|
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
|
|
case AMDGPU::OPERAND_REG_IMM_V2INT32:
|
|
case AMDGPU::OPERAND_REG_IMM_V2FP32:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
|
|
case AMDGPU::OPERAND_KIMM32:
|
|
case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
|
|
return 4;
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_INT64:
|
|
case AMDGPU::OPERAND_REG_IMM_FP64:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
|
|
return 8;
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_INT16:
|
|
case AMDGPU::OPERAND_REG_IMM_FP16:
|
|
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
|
|
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
|
|
case AMDGPU::OPERAND_REG_IMM_V2INT16:
|
|
case AMDGPU::OPERAND_REG_IMM_V2FP16:
|
|
return 2;
|
|
|
|
default:
|
|
llvm_unreachable("unhandled operand type");
|
|
}
|
|
}
|
|
|
|
LLVM_READNONE
|
|
inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
return getOperandSize(Desc.operands()[OpNo]);
|
|
}
|
|
|
|
/// Is this literal inlinable, and not one of the values intended for floating
|
|
/// point values.
|
|
LLVM_READNONE
|
|
inline bool isInlinableIntLiteral(int64_t Literal) {
|
|
return Literal >= -16 && Literal <= 64;
|
|
}
|
|
|
|
/// Is this literal inlinable
|
|
LLVM_READNONE
|
|
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
|
|
|
|
LLVM_READNONE
|
|
bool isInlinableIntLiteralV216(int32_t Literal);
|
|
|
|
LLVM_READNONE
|
|
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
|
|
|
|
bool isArgPassedInSGPR(const Argument *Arg);
|
|
|
|
bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
|
|
|
|
LLVM_READONLY
|
|
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
|
|
int64_t EncodedOffset);
|
|
|
|
LLVM_READONLY
|
|
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
|
|
int64_t EncodedOffset,
|
|
bool IsBuffer);
|
|
|
|
/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
|
|
/// offsets.
|
|
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
|
|
|
|
/// \returns The encoding that will be used for \p ByteOffset in the
|
|
/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
|
|
/// S_LOAD instructions have a signed offset, on other subtargets it is
|
|
/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
|
|
std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
|
|
int64_t ByteOffset, bool IsBuffer);
|
|
|
|
/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
|
|
/// instruction. This is only useful on CI.s
|
|
std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
|
|
int64_t ByteOffset);
|
|
|
|
/// For FLAT segment the offset must be positive;
|
|
/// MSB is ignored and forced to zero.
|
|
///
|
|
/// \return The number of bits available for the signed offset field in flat
|
|
/// instructions. Note that some forms of the instruction disallow negative
|
|
/// offsets.
|
|
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
|
|
|
|
/// \returns true if this offset is small enough to fit in the SMRD
|
|
/// offset field. \p ByteOffset should be the offset in bytes and
|
|
/// not the encoded offset.
|
|
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
|
|
|
|
LLVM_READNONE
|
|
inline bool isLegalDPALU_DPPControl(unsigned DC) {
|
|
return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
|
|
}
|
|
|
|
/// \returns true if an instruction may have a 64-bit VGPR operand.
|
|
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
|
|
|
|
/// \returns true if an instruction is a DP ALU DPP.
|
|
bool isDPALU_DPP(const MCInstrDesc &OpDesc);
|
|
|
|
/// \returns true if the intrinsic is divergent
|
|
bool isIntrinsicSourceOfDivergence(unsigned IntrID);
|
|
|
|
/// \returns true if the intrinsic is uniform
|
|
bool isIntrinsicAlwaysUniform(unsigned IntrID);
|
|
|
|
} // end namespace AMDGPU
|
|
|
|
raw_ostream &operator<<(raw_ostream &OS,
|
|
const AMDGPU::IsaInfo::TargetIDSetting S);
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
|