cda23c0732
See issue #64166 for more information about the layering issue. The PPCMCTargetDesc library was including CodeGen headers such as PPCInstrInfo.h and calling inline functions in them. This doesn't work in the Bazel build, and is error-prone. If the inline function moves to a cpp file, it will result in linker errors. To address the issue, I moved several inline functions to PPCMCTargetDesc.cpp, and declared them in the PPC namespace in PPCMCTargetDesc.h, which seemed like the most straightforward fix. Differential Revision: https://reviews.llvm.org/D156488
543 lines
20 KiB
C++
543 lines
20 KiB
C++
//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPCMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCMCCodeEmitter.h"
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#include "MCTargetDesc/PPCFixupKinds.h"
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#include "PPCMCTargetDesc.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/Triple.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx) {
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return new PPCMCCodeEmitter(MCII, Ctx);
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}
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unsigned PPCMCCodeEmitter::
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getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(isNoTOCCallInstr(MI)
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? (MCFixupKind)PPC::fixup_ppc_br24_notoc
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: (MCFixupKind)PPC::fixup_ppc_br24)));
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return 0;
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}
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/// Check if Opcode corresponds to a call instruction that should be marked
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/// with the NOTOC relocation.
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bool PPCMCCodeEmitter::isNoTOCCallInstr(const MCInst &MI) const {
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unsigned Opcode = MI.getOpcode();
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if (!MCII.get(Opcode).isCall())
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return false;
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switch (Opcode) {
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default:
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#ifndef NDEBUG
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llvm_unreachable("Unknown call opcode");
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#endif
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return false;
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case PPC::BL8_NOTOC:
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case PPC::BL8_NOTOC_TLS:
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case PPC::BL8_NOTOC_RM:
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return true;
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#ifndef NDEBUG
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case PPC::BL8:
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case PPC::BL:
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case PPC::BL8_TLS:
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case PPC::BL_TLS:
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case PPC::BLA8:
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case PPC::BLA:
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case PPC::BCCL:
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case PPC::BCCLA:
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case PPC::BCL:
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case PPC::BCLn:
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case PPC::BL8_NOP:
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case PPC::BL_NOP:
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case PPC::BL8_NOP_TLS:
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case PPC::BLA8_NOP:
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case PPC::BCTRL8:
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case PPC::BCTRL:
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case PPC::BCCCTRL8:
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case PPC::BCCCTRL:
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case PPC::BCCTRL8:
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case PPC::BCCTRL:
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case PPC::BCCTRL8n:
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case PPC::BCCTRLn:
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case PPC::BL8_RM:
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case PPC::BLA8_RM:
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case PPC::BL8_NOP_RM:
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case PPC::BLA8_NOP_RM:
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case PPC::BCTRL8_RM:
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case PPC::BCTRL8_LDinto_toc:
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case PPC::BCTRL8_LDinto_toc_RM:
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case PPC::BL8_TLS_:
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case PPC::TCRETURNdi8:
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case PPC::TCRETURNai8:
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case PPC::TCRETURNri8:
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case PPC::TAILBCTR8:
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case PPC::TAILB8:
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case PPC::TAILBA8:
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case PPC::BCLalways:
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case PPC::BLRL:
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case PPC::BCCLRL:
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case PPC::BCLRL:
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case PPC::BCLRLn:
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case PPC::BDZL:
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case PPC::BDNZL:
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case PPC::BDZLA:
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case PPC::BDNZLA:
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case PPC::BDZLp:
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case PPC::BDNZLp:
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case PPC::BDZLAp:
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case PPC::BDNZLAp:
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case PPC::BDZLm:
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case PPC::BDNZLm:
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case PPC::BDZLAm:
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case PPC::BDNZLAm:
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case PPC::BDZLRL:
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case PPC::BDNZLRL:
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case PPC::BDZLRLp:
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case PPC::BDNZLRLp:
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case PPC::BDZLRLm:
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case PPC::BDNZLRLm:
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case PPC::BL_RM:
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case PPC::BLA_RM:
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case PPC::BL_NOP_RM:
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case PPC::BCTRL_RM:
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case PPC::TCRETURNdi:
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case PPC::TCRETURNai:
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case PPC::TCRETURNri:
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case PPC::BCTRL_LWZinto_toc:
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case PPC::BCTRL_LWZinto_toc_RM:
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case PPC::TAILBCTR:
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case PPC::TAILB:
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case PPC::TAILBA:
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return false;
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#endif
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}
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}
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unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_brcond14));
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return 0;
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}
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unsigned PPCMCCodeEmitter::
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getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_br24abs));
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return 0;
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}
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unsigned PPCMCCodeEmitter::
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getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_brcond14abs));
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return 0;
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}
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unsigned
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PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
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<< 1;
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the immediate field.
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Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_half16));
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return 0;
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}
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uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI,
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MCFixupKind Fixup) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(!MO.isReg() && "Not expecting a register for this operand.");
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if (MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the immediate field.
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
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return 0;
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}
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uint64_t
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PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getImm34Encoding(MI, OpNo, Fixups, STI,
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(MCFixupKind)PPC::fixup_ppc_imm34);
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}
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uint64_t
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PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return getImm34Encoding(MI, OpNo, Fixups, STI,
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(MCFixupKind)PPC::fixup_ppc_pcrel34);
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}
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unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_half16));
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return 0;
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}
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unsigned
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PPCMCCodeEmitter::getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_half16ds));
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return 0;
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}
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unsigned
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PPCMCCodeEmitter::getDispRIX16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm()) {
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assert(!(MO.getImm() % 16) &&
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"Expecting an immediate that is a multiple of 16");
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return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);
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}
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// Otherwise add a fixup for the displacement field.
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Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_half16dq));
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return 0;
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}
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unsigned
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PPCMCCodeEmitter::getDispRIHashEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode imm for the hash load/store to stack for the ROP Protection
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// instructions.
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm() && "Expecting an immediate operand.");
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assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
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unsigned DX = (MO.getImm() >> 3) & 0x3F;
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return DX;
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}
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uint64_t
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PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode the displacement part of pc-relative memri34, which is an imm34.
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// The 34 bit immediate can fall into one of three cases:
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// 1) It is a relocation to be filled in by the linker represented as:
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// (MCExpr::SymbolRef)
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// 2) It is a relocation + SignedOffset represented as:
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// (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
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// 3) It is a known value at compile time.
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// If this is not a MCExpr then we are in case 3) and we are dealing with
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// a value known at compile time, not a relocation.
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const MCOperand &MO = MI.getOperand(OpNo);
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if (!MO.isExpr())
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return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
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// At this point in the function it is known that MO is of type MCExpr.
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// Therefore we are dealing with either case 1) a symbol ref or
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// case 2) a symbol ref plus a constant.
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const MCExpr *Expr = MO.getExpr();
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switch (Expr->getKind()) {
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default:
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llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
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case MCExpr::SymbolRef: {
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// Relocation alone.
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const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
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(void)SRE;
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// Currently these are the only valid PCRelative Relocations.
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assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
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SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL ||
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SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL ||
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SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL ||
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SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL) &&
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"VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
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"VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
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"VK_PPC_GOT_TPREL_PCREL.");
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// Generate the fixup for the relocation.
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Fixups.push_back(
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MCFixup::create(0, Expr,
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static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
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// Put zero in the location of the immediate. The linker will fill in the
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// correct value based on the relocation.
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return 0;
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}
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case MCExpr::Binary: {
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// Relocation plus some offset.
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const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
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assert(BE->getOpcode() == MCBinaryExpr::Add &&
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"Binary expression opcode must be an add.");
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const MCExpr *LHS = BE->getLHS();
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const MCExpr *RHS = BE->getRHS();
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// Need to check in both directions. Reloc+Offset and Offset+Reloc.
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if (LHS->getKind() != MCExpr::SymbolRef)
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std::swap(LHS, RHS);
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if (LHS->getKind() != MCExpr::SymbolRef ||
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RHS->getKind() != MCExpr::Constant)
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llvm_unreachable("Expecting to have one constant and one relocation.");
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const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
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(void)SRE;
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assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) &&
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"Value must fit in 34 bits.");
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// Currently these are the only valid PCRelative Relocations.
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assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
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SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
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"VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
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// Generate the fixup for the relocation.
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Fixups.push_back(
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MCFixup::create(0, Expr,
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static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
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// Put zero in the location of the immediate. The linker will fill in the
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// correct value based on the relocation.
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return 0;
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}
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}
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}
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uint64_t
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PPCMCCodeEmitter::getDispRI34Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode the displacement part of a memri34.
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const MCOperand &MO = MI.getOperand(OpNo);
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return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
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}
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unsigned
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PPCMCCodeEmitter::getDispSPE8Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode imm as a dispSPE8, which has the low 5-bits of (imm / 8).
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm());
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return getMachineOpValue(MI, MO, Fixups, STI) >> 3;
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}
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unsigned
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PPCMCCodeEmitter::getDispSPE4Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode imm as a dispSPE8, which has the low 5-bits of (imm / 4).
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm());
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return getMachineOpValue(MI, MO, Fixups, STI) >> 2;
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}
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unsigned
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PPCMCCodeEmitter::getDispSPE2Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode imm as a dispSPE8, which has the low 5-bits of (imm / 2).
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm());
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return getMachineOpValue(MI, MO, Fixups, STI) >> 1;
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}
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unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
|
|
|
|
// Add a fixup for the TLS register, which simply provides a relocation
|
|
// hint to the linker that this statement is part of a relocation sequence.
|
|
// Return the thread-pointer register's encoding. Add a one byte displacement
|
|
// if using PC relative memops.
|
|
const MCExpr *Expr = MO.getExpr();
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|
const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
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|
bool IsPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL;
|
|
Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
|
|
(MCFixupKind)PPC::fixup_ppc_nofixup));
|
|
const Triple &TT = STI.getTargetTriple();
|
|
bool isPPC64 = TT.isPPC64();
|
|
return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
|
|
}
|
|
|
|
unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
// For special TLS calls, we need two fixups; one for the branch target
|
|
// (__tls_get_addr), which we create via getDirectBrEncoding as usual,
|
|
// and one for the TLSGD or TLSLD symbol, which is emitted here.
|
|
const MCOperand &MO = MI.getOperand(OpNo+1);
|
|
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
|
|
(MCFixupKind)PPC::fixup_ppc_nofixup));
|
|
return getDirectBrEncoding(MI, OpNo, Fixups, STI);
|
|
}
|
|
|
|
unsigned PPCMCCodeEmitter::
|
|
get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
|
|
MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
|
|
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
|
|
return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
|
|
}
|
|
|
|
// Get the index for this operand in this instruction. This is needed for
|
|
// computing the register number in PPC::getRegNumForOperand() for
|
|
// any instructions that use a different numbering scheme for registers in
|
|
// different operands.
|
|
static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
|
|
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
|
|
const MCOperand &Op = MI.getOperand(i);
|
|
if (&Op == &MO)
|
|
return i;
|
|
}
|
|
llvm_unreachable("This operand is not part of this instruction");
|
|
return ~0U; // Silence any warnings about no return.
|
|
}
|
|
|
|
uint64_t PPCMCCodeEmitter::
|
|
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
if (MO.isReg()) {
|
|
// MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
|
|
// The GPR operand should come through here though.
|
|
assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
|
|
MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
|
|
MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
|
|
unsigned OpNo = getOpIdxForMO(MI, MO);
|
|
unsigned Reg =
|
|
PPC::getRegNumForOperand(MCII.get(MI.getOpcode()), MO.getReg(), OpNo);
|
|
return CTX.getRegisterInfo()->getEncodingValue(Reg);
|
|
}
|
|
|
|
assert(MO.isImm() &&
|
|
"Relocation required in an instruction that we cannot encode!");
|
|
return MO.getImm();
|
|
}
|
|
|
|
void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI,
|
|
SmallVectorImpl<char> &CB,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
|
|
|
|
// Output the constant in big/little endian byte order.
|
|
unsigned Size = getInstSizeInBytes(MI);
|
|
support::endianness E = IsLittleEndian ? support::little : support::big;
|
|
switch (Size) {
|
|
case 0:
|
|
break;
|
|
case 4:
|
|
support::endian::write<uint32_t>(CB, Bits, E);
|
|
break;
|
|
case 8:
|
|
// If we emit a pair of instructions, the first one is
|
|
// always in the top 32 bits, even on little-endian.
|
|
support::endian::write<uint32_t>(CB, Bits >> 32, E);
|
|
support::endian::write<uint32_t>(CB, Bits, E);
|
|
break;
|
|
default:
|
|
llvm_unreachable("Invalid instruction size");
|
|
}
|
|
|
|
++MCNumEmitted; // Keep track of the # of mi's emitted.
|
|
}
|
|
|
|
// Get the number of bytes used to encode the given MCInst.
|
|
unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
|
|
unsigned Opcode = MI.getOpcode();
|
|
const MCInstrDesc &Desc = MCII.get(Opcode);
|
|
return Desc.getSize();
|
|
}
|
|
|
|
bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {
|
|
return MCII.get(MI.getOpcode()).TSFlags & PPCII::Prefixed;
|
|
}
|
|
|
|
#include "PPCGenMCCodeEmitter.inc"
|