776d50d371
Make sure that the upper bits of the offset is placed in bits 20-21 of the instruction word. This fixes the encoding of backwards (negative offset) BPr branches. (Previously, the upper two bits of the offset would overwrite parts of the rs1 field, causing it to branch on the wrong register, with the wrong offset) Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D144012
378 lines
14 KiB
C++
378 lines
14 KiB
C++
//===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SparcFixupKinds.h"
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#include "MCTargetDesc/SparcMCTargetDesc.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/EndianStream.h"
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using namespace llvm;
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return Value;
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case Sparc::fixup_sparc_wplt30:
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case Sparc::fixup_sparc_call30:
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return (Value >> 2) & 0x3fffffff;
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case Sparc::fixup_sparc_br22:
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return (Value >> 2) & 0x3fffff;
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case Sparc::fixup_sparc_br19:
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return (Value >> 2) & 0x7ffff;
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case Sparc::fixup_sparc_br16: {
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// A.3 Branch on Integer Register with Prediction (BPr)
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// Inst{21-20} = d16hi;
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// Inst{13-0} = d16lo;
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unsigned d16hi = (Value >> 16) & 0x3;
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unsigned d16lo = (Value >> 2) & 0x3fff;
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return (d16hi << 20) | d16lo;
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}
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case Sparc::fixup_sparc_hix22:
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return (~Value >> 10) & 0x3fffff;
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case Sparc::fixup_sparc_pc22:
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case Sparc::fixup_sparc_got22:
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case Sparc::fixup_sparc_tls_gd_hi22:
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case Sparc::fixup_sparc_tls_ldm_hi22:
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case Sparc::fixup_sparc_tls_ie_hi22:
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case Sparc::fixup_sparc_hi22:
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case Sparc::fixup_sparc_lm:
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return (Value >> 10) & 0x3fffff;
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case Sparc::fixup_sparc_got13:
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case Sparc::fixup_sparc_13:
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return Value & 0x1fff;
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case Sparc::fixup_sparc_lox10:
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return (Value & 0x3ff) | 0x1c00;
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case Sparc::fixup_sparc_pc10:
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case Sparc::fixup_sparc_got10:
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case Sparc::fixup_sparc_tls_gd_lo10:
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case Sparc::fixup_sparc_tls_ldm_lo10:
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case Sparc::fixup_sparc_tls_ie_lo10:
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case Sparc::fixup_sparc_lo10:
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return Value & 0x3ff;
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case Sparc::fixup_sparc_h44:
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return (Value >> 22) & 0x3fffff;
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case Sparc::fixup_sparc_m44:
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return (Value >> 12) & 0x3ff;
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case Sparc::fixup_sparc_l44:
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return Value & 0xfff;
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case Sparc::fixup_sparc_hh:
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return (Value >> 42) & 0x3fffff;
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case Sparc::fixup_sparc_hm:
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return (Value >> 32) & 0x3ff;
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case Sparc::fixup_sparc_tls_ldo_hix22:
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case Sparc::fixup_sparc_tls_le_hix22:
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case Sparc::fixup_sparc_tls_ldo_lox10:
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case Sparc::fixup_sparc_tls_le_lox10:
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assert(Value == 0 && "Sparc TLS relocs expect zero Value");
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return 0;
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case Sparc::fixup_sparc_tls_gd_add:
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case Sparc::fixup_sparc_tls_gd_call:
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case Sparc::fixup_sparc_tls_ldm_add:
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case Sparc::fixup_sparc_tls_ldm_call:
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case Sparc::fixup_sparc_tls_ldo_add:
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case Sparc::fixup_sparc_tls_ie_ld:
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case Sparc::fixup_sparc_tls_ie_ldx:
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case Sparc::fixup_sparc_tls_ie_add:
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case Sparc::fixup_sparc_gotdata_lox10:
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case Sparc::fixup_sparc_gotdata_hix22:
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case Sparc::fixup_sparc_gotdata_op:
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return 0;
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}
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}
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/// getFixupKindNumBytes - The number of bytes the fixup may change.
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default:
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return 4;
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case FK_Data_1:
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return 1;
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case FK_Data_2:
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return 2;
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case FK_Data_8:
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return 8;
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}
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}
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namespace {
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class SparcAsmBackend : public MCAsmBackend {
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protected:
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const Target &TheTarget;
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bool Is64Bit;
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public:
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SparcAsmBackend(const Target &T)
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: MCAsmBackend(StringRef(T.getName()) == "sparcel" ? support::little
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: support::big),
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TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
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unsigned getNumFixupKinds() const override {
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return Sparc::NumTargetFixupKinds;
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}
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std::optional<MCFixupKind> getFixupKind(StringRef Name) const override {
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unsigned Type;
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Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#include "llvm/BinaryFormat/ELFRelocs/Sparc.def"
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#undef ELF_RELOC
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.Case("BFD_RELOC_NONE", ELF::R_SPARC_NONE)
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.Case("BFD_RELOC_8", ELF::R_SPARC_8)
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.Case("BFD_RELOC_16", ELF::R_SPARC_16)
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.Case("BFD_RELOC_32", ELF::R_SPARC_32)
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.Case("BFD_RELOC_64", ELF::R_SPARC_64)
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.Default(-1u);
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if (Type == -1u)
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return std::nullopt;
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return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br16", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_13", 19, 13, 0 },
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{ "fixup_sparc_hi22", 10, 22, 0 },
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{ "fixup_sparc_lo10", 22, 10, 0 },
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{ "fixup_sparc_h44", 10, 22, 0 },
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{ "fixup_sparc_m44", 22, 10, 0 },
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{ "fixup_sparc_l44", 20, 12, 0 },
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{ "fixup_sparc_hh", 10, 22, 0 },
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{ "fixup_sparc_hm", 22, 10, 0 },
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{ "fixup_sparc_lm", 10, 22, 0 },
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{ "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_got22", 10, 22, 0 },
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{ "fixup_sparc_got10", 22, 10, 0 },
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{ "fixup_sparc_got13", 19, 13, 0 },
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{ "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
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{ "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
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{ "fixup_sparc_tls_gd_add", 0, 0, 0 },
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{ "fixup_sparc_tls_gd_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
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{ "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
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{ "fixup_sparc_tls_ldm_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
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{ "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
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{ "fixup_sparc_tls_ldo_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
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{ "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
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{ "fixup_sparc_tls_ie_ld", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_add", 0, 0, 0 },
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{ "fixup_sparc_tls_le_hix22", 0, 0, 0 },
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{ "fixup_sparc_tls_le_lox10", 0, 0, 0 },
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{ "fixup_sparc_hix22", 10, 22, 0 },
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{ "fixup_sparc_lox10", 19, 13, 0 },
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{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
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{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
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{ "fixup_sparc_gotdata_op", 0, 0, 0 },
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};
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const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_br16", 32, 0, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_13", 0, 13, 0 },
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{ "fixup_sparc_hi22", 0, 22, 0 },
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{ "fixup_sparc_lo10", 0, 10, 0 },
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{ "fixup_sparc_h44", 0, 22, 0 },
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{ "fixup_sparc_m44", 0, 10, 0 },
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{ "fixup_sparc_l44", 0, 12, 0 },
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{ "fixup_sparc_hh", 0, 22, 0 },
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{ "fixup_sparc_hm", 0, 10, 0 },
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{ "fixup_sparc_lm", 0, 22, 0 },
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{ "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_got22", 0, 22, 0 },
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{ "fixup_sparc_got10", 0, 10, 0 },
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{ "fixup_sparc_got13", 0, 13, 0 },
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{ "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_sparc_tls_gd_hi22", 0, 22, 0 },
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{ "fixup_sparc_tls_gd_lo10", 0, 10, 0 },
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{ "fixup_sparc_tls_gd_add", 0, 0, 0 },
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{ "fixup_sparc_tls_gd_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_hi22", 0, 22, 0 },
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{ "fixup_sparc_tls_ldm_lo10", 0, 10, 0 },
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{ "fixup_sparc_tls_ldm_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ldm_call", 0, 0, 0 },
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{ "fixup_sparc_tls_ldo_hix22", 0, 22, 0 },
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{ "fixup_sparc_tls_ldo_lox10", 0, 10, 0 },
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{ "fixup_sparc_tls_ldo_add", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_hi22", 0, 22, 0 },
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{ "fixup_sparc_tls_ie_lo10", 0, 10, 0 },
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{ "fixup_sparc_tls_ie_ld", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
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{ "fixup_sparc_tls_ie_add", 0, 0, 0 },
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{ "fixup_sparc_tls_le_hix22", 0, 0, 0 },
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{ "fixup_sparc_tls_le_lox10", 0, 0, 0 },
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{ "fixup_sparc_hix22", 0, 22, 0 },
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{ "fixup_sparc_lox10", 0, 13, 0 },
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{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
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{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
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{ "fixup_sparc_gotdata_op", 0, 0, 0 },
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};
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// Fixup kinds from .reloc directive are like R_SPARC_NONE. They do
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// not require any extra processing.
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if (Kind >= FirstLiteralRelocationKind)
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return MCAsmBackend::getFixupKindInfo(FK_NONE);
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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if (Endian == support::little)
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return InfosLE[Kind - FirstTargetFixupKind];
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return InfosBE[Kind - FirstTargetFixupKind];
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}
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bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target) override {
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if (Fixup.getKind() >= FirstLiteralRelocationKind)
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return true;
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switch ((Sparc::Fixups)Fixup.getKind()) {
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default:
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return false;
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case Sparc::fixup_sparc_wplt30:
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if (Target.getSymA()->getSymbol().isTemporary())
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return false;
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[[fallthrough]];
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case Sparc::fixup_sparc_tls_gd_hi22:
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case Sparc::fixup_sparc_tls_gd_lo10:
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case Sparc::fixup_sparc_tls_gd_add:
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case Sparc::fixup_sparc_tls_gd_call:
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case Sparc::fixup_sparc_tls_ldm_hi22:
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case Sparc::fixup_sparc_tls_ldm_lo10:
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case Sparc::fixup_sparc_tls_ldm_add:
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case Sparc::fixup_sparc_tls_ldm_call:
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case Sparc::fixup_sparc_tls_ldo_hix22:
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case Sparc::fixup_sparc_tls_ldo_lox10:
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case Sparc::fixup_sparc_tls_ldo_add:
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case Sparc::fixup_sparc_tls_ie_hi22:
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case Sparc::fixup_sparc_tls_ie_lo10:
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case Sparc::fixup_sparc_tls_ie_ld:
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case Sparc::fixup_sparc_tls_ie_ldx:
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case Sparc::fixup_sparc_tls_ie_add:
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case Sparc::fixup_sparc_tls_le_hix22:
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case Sparc::fixup_sparc_tls_le_lox10:
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return true;
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}
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}
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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/// fixup requires the associated instruction to be relaxed.
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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// FIXME.
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llvm_unreachable("fixupNeedsRelaxation() unimplemented");
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return false;
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}
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void relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const override {
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// FIXME.
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llvm_unreachable("relaxInstruction() unimplemented");
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}
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bool writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const override {
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// Cannot emit NOP with size not multiple of 32 bits.
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if (Count % 4 != 0)
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return false;
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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support::endian::write<uint32_t>(OS, 0x01000000, Endian);
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return true;
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}
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};
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class ELFSparcAsmBackend : public SparcAsmBackend {
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Triple::OSType OSType;
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public:
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ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
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SparcAsmBackend(T), OSType(OSType) { }
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override {
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if (Fixup.getKind() >= FirstLiteralRelocationKind)
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return;
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Value = adjustFixupValue(Fixup.getKind(), Value);
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if (!Value) return; // Doesn't change encoding.
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unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
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unsigned Offset = Fixup.getOffset();
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// For each byte of the fragment that the fixup touches, mask in the bits
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// from the fixup value. The Value has been "split up" into the
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// appropriate bitfields above.
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i;
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Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
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}
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}
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override {
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
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return createSparcELFObjectWriter(Is64Bit, OSABI);
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}
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};
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} // end anonymous namespace
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MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
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}
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