Craig Topper 8677aaa1a3 [RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.

2023-09-18 10:59:00 -07:00

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AArch64

[AArch64] Remove the Z#_HI register definitions (#66353)

2023-09-18 17:18:28 +01:00

AMDGPU

[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register

2023-09-15 19:52:50 +00:00

ARC

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ARM

Revert "[ARM] Always lower direct calls as direct when the outliner is enabled (#66434)"

2023-09-18 09:45:46 -07:00

AVR

[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register

2023-09-15 19:52:50 +00:00

BPF

Revert "Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size"

2023-09-18 17:24:53 +02:00

CSKY

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DirectX

[DirectX backend] avoid generate redundant bitcast in DXILPrepareModule (#65163)

2023-09-01 20:08:39 -04:00

Generic

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Hexagon

[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register

2023-09-15 19:52:50 +00:00

Inputs

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Lanai

[test] Change llc -march= to -mtriple= & llvm-mc -arch= to -triple=

2023-09-11 15:11:01 -07:00

LoongArch

[LoongArch] Fix incorrect instruction 'and' in pattern

2023-09-15 16:16:06 +08:00

M68k

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Mips

[SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs

2023-09-16 17:09:41 +08:00

MIR

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MLRegAlloc

[mlgo] Fix regalloc tests

2023-09-15 17:27:34 -04:00

MSP430

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NVPTX

[NVPTX] Tighten up legal v2i16 ops a bit

2023-09-12 16:10:20 +02:00

PowerPC

[SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. (#66601)

2023-09-18 08:58:50 -07:00

RISCV

[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.

2023-09-18 10:59:00 -07:00

SPARC

[Sparc] Don't emit __multi3 on 32-bit SPARC (#66362)

2023-09-15 07:31:59 +02:00

SPIRV

[SPIR-V] Support SPV_INTEL_arbitrary_precision_integers_extension, misc utils for other extensions

2023-09-12 02:45:15 -07:00

SystemZ

Add some -early-live-intervals RUN lines (#66058)

2023-09-12 13:06:10 +01:00

Thumb

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Thumb2

[TwoAddressInstruction] Update LiveIntervals after INSERT_SUBREG with undef read (#66211)

2023-09-18 14:51:58 +01:00

VE

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WebAssembly

[IR] Remove unnecessary bitcast from CreateMalloc()

2023-09-18 14:58:16 +02:00

WinCFGuard

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WinEH

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X86

Revert "Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size"

2023-09-18 17:24:53 +02:00

XCore

[test] Change llc -march= to -mtriple=

2023-09-11 14:42:37 -07:00