Matthias Springer 15ea2306a4 [mlir][NVGPU] Support N-D masks in transform.nvgpu.create_async_groups ...

Support IR that is generated by the vector-to-scf lowering of N-D vector transfers with a mask. (Until now only 1-D and 2-D transfers were supported.) Only transfers that were fully unrolled are supported.

Differential Revision: https://reviews.llvm.org/D157286

2023-08-08 14:30:03 +02:00

..

CMakeLists.txt

[mlir][NVGPU][transform] Add create_async_groups transform op

2023-07-18 14:36:41 +02:00

CreateAsyncGroups.cpp

[mlir][NVGPU] Support N-D masks in transform.nvgpu.create_async_groups

2023-08-08 14:30:03 +02:00

MmaSyncTF32Transform.cpp

[mlir][NVGPU][NFC] Clean up code structure

2023-07-17 14:15:42 +02:00

OptimizeSharedMemory.cpp

[mlir][NVGPU][NFC] Clean up code structure

2023-07-17 14:15:42 +02:00

Utils.cpp

[mlir][NVGPU][transform] Add create_async_groups transform op

2023-07-18 14:36:41 +02:00