5093413a50
This patch adds an NVPTX compilation path that enables JIT compilation on NVIDIA targets. The following modifications were performed: 1. Adding a format field to the GPU object attribute, allowing the translation attribute to use the correct runtime function to load the module. Likewise, a dictionary attribute was added to add any possible extra options. 2. Adding the `createObject` method to `GPUTargetAttrInterface`; this method returns a GPU object from a binary string. 3. Adding the function `mgpuModuleLoadJIT`, which is only available for NVIDIA GPUs, as there is no equivalent for AMD. 4. Adding the CMake flag `MLIR_GPU_COMPILATION_TEST_FORMAT` to specify the format to use during testing.
107 lines
4.9 KiB
C++
107 lines
4.9 KiB
C++
//===- SparseTensorPipelines.cpp - Pipelines for sparse tensor code -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/SparseTensor/Pipelines/Passes.h"
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#include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h"
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#include "mlir/Conversion/Passes.h"
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#include "mlir/Dialect/Arith/Transforms/Passes.h"
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#include "mlir/Dialect/Bufferization/Transforms/Bufferize.h"
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#include "mlir/Dialect/Bufferization/Transforms/OneShotAnalysis.h"
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#include "mlir/Dialect/Bufferization/Transforms/Passes.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/GPU/Transforms/Passes.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/Dialect/Linalg/Passes.h"
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#include "mlir/Dialect/MemRef/Transforms/Passes.h"
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#include "mlir/Dialect/SparseTensor/IR/SparseTensor.h"
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#include "mlir/Dialect/SparseTensor/Transforms/Passes.h"
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#include "mlir/Pass/PassManager.h"
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#include "mlir/Transforms/Passes.h"
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//===----------------------------------------------------------------------===//
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// Pipeline implementation.
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//===----------------------------------------------------------------------===//
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void mlir::sparse_tensor::buildSparseCompiler(
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OpPassManager &pm, const SparseCompilerOptions &options) {
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pm.addNestedPass<func::FuncOp>(createLinalgGeneralizationPass());
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pm.addPass(createSparsificationAndBufferizationPass(
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getBufferizationOptionsForSparsification(
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options.testBufferizationAnalysisOnly),
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options.sparsificationOptions(), options.sparseTensorConversionOptions(),
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options.createSparseDeallocs, options.enableRuntimeLibrary,
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options.enableBufferInitialization, options.vectorLength,
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/*enableVLAVectorization=*/options.armSVE,
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/*enableSIMDIndex32=*/options.force32BitVectorIndices));
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if (options.testBufferizationAnalysisOnly)
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return;
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pm.addNestedPass<func::FuncOp>(createCanonicalizerPass());
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pm.addNestedPass<func::FuncOp>(
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mlir::bufferization::createFinalizingBufferizePass());
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// GPU code generation.
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const bool gpuCodegen = options.gpuTriple.hasValue();
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if (gpuCodegen) {
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pm.addPass(createSparseGPUCodegenPass());
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pm.addNestedPass<gpu::GPUModuleOp>(createStripDebugInfoPass());
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pm.addNestedPass<gpu::GPUModuleOp>(createConvertSCFToCFPass());
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pm.addNestedPass<gpu::GPUModuleOp>(createConvertGpuOpsToNVVMOps());
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}
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// TODO(springerm): Add sparse support to the BufferDeallocation pass and add
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// it to this pipeline.
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pm.addNestedPass<func::FuncOp>(createConvertLinalgToLoopsPass());
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pm.addNestedPass<func::FuncOp>(createConvertVectorToSCFPass());
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pm.addNestedPass<func::FuncOp>(memref::createExpandReallocPass());
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pm.addNestedPass<func::FuncOp>(createConvertSCFToCFPass());
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pm.addPass(memref::createExpandStridedMetadataPass());
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pm.addPass(createLowerAffinePass());
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pm.addPass(createConvertVectorToLLVMPass(options.lowerVectorToLLVMOptions()));
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pm.addPass(createFinalizeMemRefToLLVMConversionPass());
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pm.addNestedPass<func::FuncOp>(createConvertComplexToStandardPass());
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pm.addNestedPass<func::FuncOp>(arith::createArithExpandOpsPass());
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pm.addNestedPass<func::FuncOp>(createConvertMathToLLVMPass());
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pm.addPass(createConvertMathToLibmPass());
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pm.addPass(createConvertComplexToLibmPass());
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// Repeat convert-vector-to-llvm.
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pm.addPass(createConvertVectorToLLVMPass(options.lowerVectorToLLVMOptions()));
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pm.addPass(createConvertComplexToLLVMPass());
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pm.addPass(createConvertVectorToLLVMPass(options.lowerVectorToLLVMOptions()));
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pm.addPass(createConvertFuncToLLVMPass());
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// Finalize GPU code generation.
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if (gpuCodegen) {
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GpuNVVMAttachTargetOptions nvvmTargetOptions;
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nvvmTargetOptions.triple = options.gpuTriple;
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nvvmTargetOptions.chip = options.gpuChip;
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nvvmTargetOptions.features = options.gpuFeatures;
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pm.addPass(createGpuNVVMAttachTarget(nvvmTargetOptions));
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pm.addPass(createGpuToLLVMConversionPass());
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GpuModuleToBinaryPassOptions gpuModuleToBinaryPassOptions;
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gpuModuleToBinaryPassOptions.compilationTarget = options.gpuFormat;
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pm.addPass(createGpuModuleToBinaryPass(gpuModuleToBinaryPassOptions));
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}
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pm.addPass(createReconcileUnrealizedCastsPass());
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}
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//===----------------------------------------------------------------------===//
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// Pipeline registration.
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//===----------------------------------------------------------------------===//
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void mlir::sparse_tensor::registerSparseTensorPipelines() {
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PassPipelineRegistration<SparseCompilerOptions>(
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"sparse-compiler",
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"The standard pipeline for taking sparsity-agnostic IR using the"
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" sparse-tensor type, and lowering it to LLVM IR with concrete"
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" representations and algorithms for sparse tensors.",
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buildSparseCompiler);
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}
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