dbcfbffc7a
This patch introduces two intrinsics: llvm.ppc.setflm and llvm.ppc.readflm. They read from or write to FPSCR register (floating-point status & control) which contains rounding mode and exception status. To ensure correctness of program, we need to prevent FP operations from being moved across these intrinsics (mffs/mtfsf instruction), so here I set them as scheduling boundaries. We can relax such restriction if FPSCR is modeled well in the future. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D84914
82 lines
3.2 KiB
LLVM
82 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple powerpc64le-unknown-linux | FileCheck %s
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; RUN: llc < %s -mtriple powerpc64le-unknown-linux -debug-only=machine-scheduler \
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; RUN: 2>&1 | FileCheck %s --check-prefix=LOG
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define double @in_nostrict(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: in_nostrict:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: xsdivdp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 1, 3
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; CHECK-NEXT: xsadddp 0, 1, 0
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; CHECK-NEXT: mtfsf 255, 4
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; CHECK-NEXT: xsdivdp 1, 3, 4
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; CHECK-NEXT: xsadddp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 0, 1
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; CHECK-NEXT: blr
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;
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; LOG: *** MI Scheduling ***
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; LOG-NEXT: in_nostrict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, %{{[0-9]+}}:f8rc, 0, 0
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; LOG: *** MI Scheduling ***
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; LOG-NEXT: in_nostrict:%bb.0 entry
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; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
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;
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; LOG: *** MI Scheduling ***
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; LOG-NEXT: in_nostrict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, renamable $f{{[0-9]+}}, 0, 0
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entry:
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%0 = tail call double @llvm.ppc.readflm()
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%1 = fdiv double %a, %b
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%2 = fadd double %1, %c
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%3 = fadd double %2, %0
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call double @llvm.ppc.setflm(double %d)
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%5 = fdiv double %c, %d
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%6 = fadd double %5, %b
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%7 = fadd double %3, %6
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ret double %7
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}
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define double @in_strict(double %a, double %b, double %c, double %d) #0 {
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; CHECK-LABEL: in_strict:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: xsdivdp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 1, 3
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; CHECK-NEXT: xsadddp 0, 1, 0
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; CHECK-NEXT: mtfsf 255, 4
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; CHECK-NEXT: xsdivdp 1, 3, 4
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; CHECK-NEXT: xsadddp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 0, 1
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; CHECK-NEXT: blr
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;
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; LOG: ***** MI Scheduling *****
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; LOG-NEXT: in_strict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, %{{[0-9]+}}:f8rc, 0, 0
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; LOG: ***** MI Scheduling *****
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; LOG-NEXT: in_strict:%bb.0 entry
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; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
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;
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; LOG: ***** MI Scheduling *****
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; LOG-NEXT: in_strict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, renamable $f{{[0-9]+}}, 0, 0
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entry:
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%0 = tail call double @llvm.ppc.readflm()
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%1 = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%2 = call double @llvm.experimental.constrained.fadd.f64(double %1, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%3 = call double @llvm.experimental.constrained.fadd.f64(double %2, double %0, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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call double @llvm.ppc.setflm(double %d)
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%5 = call double @llvm.experimental.constrained.fdiv.f64(double %c, double %d, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%6 = call double @llvm.experimental.constrained.fadd.f64(double %5, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%7 = call double @llvm.experimental.constrained.fadd.f64(double %3, double %6, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret double %7
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}
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declare double @llvm.ppc.readflm()
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declare double @llvm.ppc.setflm(double)
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declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
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declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
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attributes #0 = { strictfp }
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