5446ec8507
Historical modeling of the LLVM dialect types had been wrapping LLVM IR types and therefore needed access to the instance of LLVMContext stored in the LLVMDialect. The new modeling does not rely on that and only needs the MLIRContext that is used for uniquing, similarly to other MLIR types. Change LLVMType::get<Kind>Ty functions to take `MLIRContext *` instead of `LLVMDialect *` as first argument. This brings the code base closer to completely removing the dependence on LLVMContext from the LLVMDialect, together with additional support for thread-safety of its use. Depends On D85371 Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D85372
191 lines
8.6 KiB
C++
191 lines
8.6 KiB
C++
//===- LowerGpuOpsToNVVMOps.cpp - MLIR GPU to NVVM lowering passes --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to generate NVVMIR operations for higher-level
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// GPU operations.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
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#include "mlir/Dialect/GPU/GPUDialect.h"
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#include "mlir/Dialect/GPU/Passes.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/IR/BlockAndValueMapping.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "../GPUCommon/GPUOpsLowering.h"
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#include "../GPUCommon/IndexIntrinsicsOpLowering.h"
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#include "../GPUCommon/OpToFuncCallLowering.h"
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#include "../PassDetail.h"
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using namespace mlir;
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namespace {
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struct GPUShuffleOpLowering : public ConvertToLLVMPattern {
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explicit GPUShuffleOpLowering(LLVMTypeConverter &lowering_)
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: ConvertToLLVMPattern(gpu::ShuffleOp::getOperationName(),
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lowering_.getDialect()->getContext(), lowering_) {}
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/// Lowers a shuffle to the corresponding NVVM op.
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///
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/// Convert the `width` argument into an activeMask (a bitmask which specifies
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/// which threads participate in the shuffle) and a maskAndClamp (specifying
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/// the highest lane which participates in the shuffle).
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///
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/// %one = llvm.constant(1 : i32) : !llvm.i32
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/// %shl = llvm.shl %one, %width : !llvm.i32
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/// %active_mask = llvm.sub %shl, %one : !llvm.i32
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/// %mask_and_clamp = llvm.sub %width, %one : !llvm.i32
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/// %shfl = nvvm.shfl.sync.bfly %active_mask, %value, %offset,
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/// %mask_and_clamp : !llvm<"{ float, i1 }">
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/// %shfl_value = llvm.extractvalue %shfl[0 : index] :
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/// !llvm<"{ float, i1 }">
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/// %shfl_pred = llvm.extractvalue %shfl[1 : index] :
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/// !llvm<"{ float, i1 }">
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LogicalResult
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matchAndRewrite(Operation *op, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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gpu::ShuffleOpAdaptor adaptor(operands);
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auto valueTy = adaptor.value().getType().cast<LLVM::LLVMType>();
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auto int32Type = LLVM::LLVMType::getInt32Ty(rewriter.getContext());
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auto predTy = LLVM::LLVMType::getInt1Ty(rewriter.getContext());
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auto resultTy =
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LLVM::LLVMType::getStructTy(rewriter.getContext(), {valueTy, predTy});
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Value one = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(1));
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// Bit mask of active lanes: `(1 << activeWidth) - 1`.
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Value activeMask = rewriter.create<LLVM::SubOp>(
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loc, int32Type,
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rewriter.create<LLVM::ShlOp>(loc, int32Type, one, adaptor.width()),
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one);
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// Clamp lane: `activeWidth - 1`
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Value maskAndClamp =
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rewriter.create<LLVM::SubOp>(loc, int32Type, adaptor.width(), one);
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auto returnValueAndIsValidAttr = rewriter.getUnitAttr();
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Value shfl = rewriter.create<NVVM::ShflBflyOp>(
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loc, resultTy, activeMask, adaptor.value(), adaptor.offset(),
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maskAndClamp, returnValueAndIsValidAttr);
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Value shflValue = rewriter.create<LLVM::ExtractValueOp>(
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loc, valueTy, shfl, rewriter.getIndexArrayAttr(0));
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Value isActiveSrcLane = rewriter.create<LLVM::ExtractValueOp>(
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loc, predTy, shfl, rewriter.getIndexArrayAttr(1));
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rewriter.replaceOp(op, {shflValue, isActiveSrcLane});
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return success();
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}
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};
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/// Import the GPU Ops to NVVM Patterns.
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#include "GPUToNVVM.cpp.inc"
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/// A pass that replaces all occurrences of GPU device operations with their
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/// corresponding NVVM equivalent.
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///
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/// This pass only handles device code and is not meant to be run on GPU host
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/// code.
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struct LowerGpuOpsToNVVMOpsPass
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: public ConvertGpuOpsToNVVMOpsBase<LowerGpuOpsToNVVMOpsPass> {
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LowerGpuOpsToNVVMOpsPass() = default;
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LowerGpuOpsToNVVMOpsPass(unsigned indexBitwidth) {
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this->indexBitwidth = indexBitwidth;
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}
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void runOnOperation() override {
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gpu::GPUModuleOp m = getOperation();
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/// Customize the bitwidth used for the device side index computations.
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LowerToLLVMOptions options = {/*useBarePtrCallConv =*/false,
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/*emitCWrappers =*/true,
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/*indexBitwidth =*/indexBitwidth,
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/*useAlignedAlloc =*/false};
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/// MemRef conversion for GPU to NVVM lowering. The GPU dialect uses memory
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/// space 5 for private memory attributions, but NVVM represents private
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/// memory allocations as local `alloca`s in the default address space. This
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/// converter drops the private memory space to support the use case above.
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LLVMTypeConverter converter(m.getContext(), options);
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converter.addConversion([&](MemRefType type) -> Optional<Type> {
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if (type.getMemorySpace() != gpu::GPUDialect::getPrivateAddressSpace())
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return llvm::None;
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return converter.convertType(MemRefType::Builder(type).setMemorySpace(0));
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});
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OwningRewritePatternList patterns;
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// Apply in-dialect lowering first. In-dialect lowering will replace ops
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// which need to be lowered further, which is not supported by a single
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// conversion pass.
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populateGpuRewritePatterns(m.getContext(), patterns);
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applyPatternsAndFoldGreedily(m, patterns);
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patterns.clear();
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populateStdToLLVMConversionPatterns(converter, patterns);
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populateGpuToNVVMConversionPatterns(converter, patterns);
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LLVMConversionTarget target(getContext());
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target.addIllegalDialect<gpu::GPUDialect>();
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target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::FAbsOp, LLVM::FCeilOp,
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LLVM::LogOp, LLVM::Log10Op, LLVM::Log2Op>();
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target.addIllegalOp<FuncOp>();
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target.addLegalDialect<NVVM::NVVMDialect>();
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// TODO: Remove once we support replacing non-root ops.
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target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
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if (failed(applyPartialConversion(m, target, patterns)))
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signalPassFailure();
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}
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};
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} // anonymous namespace
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void mlir::populateGpuToNVVMConversionPatterns(
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LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
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populateWithGenerated(converter.getDialect()->getContext(), &patterns);
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patterns
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.insert<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, NVVM::ThreadIdXOp,
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NVVM::ThreadIdYOp, NVVM::ThreadIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, NVVM::BlockDimXOp,
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NVVM::BlockDimYOp, NVVM::BlockDimZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, NVVM::BlockIdXOp,
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NVVM::BlockIdYOp, NVVM::BlockIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::GridDimOp, NVVM::GridDimXOp,
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NVVM::GridDimYOp, NVVM::GridDimZOp>,
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GPUShuffleOpLowering, GPUReturnOpLowering,
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// Explicitly drop memory space when lowering private memory
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// attributions since NVVM models it as `alloca`s in the default
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// memory space and does not support `alloca`s with addrspace(5).
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GPUFuncOpLowering<0>>(converter);
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patterns.insert<OpToFuncCallLowering<AbsFOp>>(converter, "__nv_fabsf",
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"__nv_fabs");
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patterns.insert<OpToFuncCallLowering<CeilFOp>>(converter, "__nv_ceilf",
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"__nv_ceil");
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patterns.insert<OpToFuncCallLowering<CosOp>>(converter, "__nv_cosf",
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"__nv_cos");
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patterns.insert<OpToFuncCallLowering<ExpOp>>(converter, "__nv_expf",
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"__nv_exp");
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patterns.insert<OpToFuncCallLowering<LogOp>>(converter, "__nv_logf",
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"__nv_log");
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patterns.insert<OpToFuncCallLowering<Log10Op>>(converter, "__nv_log10f",
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"__nv_log10");
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patterns.insert<OpToFuncCallLowering<Log2Op>>(converter, "__nv_log2f",
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"__nv_log2");
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patterns.insert<OpToFuncCallLowering<TanhOp>>(converter, "__nv_tanhf",
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"__nv_tanh");
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}
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std::unique_ptr<OperationPass<gpu::GPUModuleOp>>
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mlir::createLowerGpuOpsToNVVMOpsPass(unsigned indexBitwidth) {
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return std::make_unique<LowerGpuOpsToNVVMOpsPass>(indexBitwidth);
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}
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