Sanjay Patel 58c1770b8f [x86] add test for shift+op+concat; NFC ...

D79360 could change this kind of sequence.

2020-05-04 17:31:45 -04:00

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AArch64

[AArch64] Add NVIDIA Carmel support

2020-05-04 13:52:30 +01:00

AMDGPU

[AMDGPU] fix copies between 32 and 16 bit

2020-05-04 08:54:22 -07:00

ARC

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ARM

[ARM] Fix tail call validity checking for varargs calls.

2020-05-04 12:34:14 -07:00

AVR

[AVR] Do not place functions in .progmem.data

2020-04-20 13:56:38 +02:00

BPF

BPF: fix a CORE optimization bug

2020-04-20 19:54:51 -07:00

Generic

[MachineDebugify] Insert synthetic DBG_VALUE instructions

2020-04-22 17:03:39 -07:00

Hexagon

Handle cases for subregisters.

2020-04-30 20:32:33 -05:00

Inputs

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Lanai

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Mips

[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values

2020-05-04 14:44:39 +01:00

MIR

[AMDGPU] Avoid hard-coded line numbers in error message checks

2020-04-23 21:06:09 +01:00

MSP430

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NVPTX

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PowerPC

[PowerPC][AIX][NFC] Remove spills and reloads from arg passing test.

2020-05-04 14:26:33 -04:00

RISCV

[RISCV] Implement convertSelectOfConstantsToMath

2020-05-02 15:05:57 +01:00

SPARC

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SystemZ

[SystemZ] Fix test case.

2020-04-28 09:43:03 +02:00

Thumb

[ARM] Don't shrink STM if it would cause an unknown base register store

2020-04-22 14:50:42 +01:00

Thumb2

[ARM] Complex LSR test showing inefficient codegen. NFC

2020-05-04 21:50:10 +01:00

VE

[VE] Update branch instructions

2020-04-28 09:41:01 +02:00

WebAssembly

[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values

2020-05-04 14:44:39 +01:00

WinCFGuard

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WinEH

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X86

[x86] add test for shift+op+concat; NFC

2020-05-04 17:31:45 -04:00

XCore

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