Craig Topper 1c17484e10 [RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRAI64_HINT. (#112250) ...

c.srli(64) and c.srai(64) are encoded differently than c.slli(64). The
former have a 3-bit register, while the latter has a 5-bit register.
c.srli and c.srai already use RVInst16CB.

The "let Inst{11-10} =" prevented this from causing any functional
issues by dropping the upper 2 bits of the register. The ins/outs list
uses GPRC so the register class is constrained.

2024-10-14 15:25:29 -07:00

..

AsmParser

[RISCV] Support Expressions in .insn Directives (#111893)

2024-10-14 14:07:35 +01:00

Disassembler

[RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)

2024-10-06 19:27:18 -07:00

GISel

[RISCV][GISEL][NFC] Add break statement to reduce diff on future changes of preISelLower

2024-10-07 07:23:52 -07:00

MCA

…

MCTargetDesc

[RISCV][MC] Fix >32bit .insn Directives (#111878)

2024-10-11 12:24:54 +01:00

TargetInfo

…

CMakeLists.txt

[RISCV] Introduce VLOptimizer pass (#108640)

2024-10-11 09:45:35 -04:00

RISCV.h

[RISCV] Introduce VLOptimizer pass (#108640)

2024-10-11 09:45:35 -04:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814)

2024-09-17 18:52:55 +03:00

RISCVAsmPrinter.cpp

[RISCV] Use RISCVAsmPrinter::EmitToStreamer for EmitHwasanMemaccessSymbols. (#111792)

2024-10-10 08:43:30 -07:00

RISCVCallingConv.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVCallingConv.h

[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)

2024-09-06 09:28:33 -07:00

RISCVCallingConv.td

…

RISCVCodeGenPrepare.cpp

[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329)

2024-08-01 09:37:42 +08:00

RISCVCombine.td

Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"

2024-09-20 07:01:17 -07:00

RISCVConstantPoolValue.cpp

[RISCV] Support the large code model. (#70308)

2024-09-09 09:15:07 +08:00

RISCVConstantPoolValue.h

[RISCV] Support the large code model. (#70308)

2024-09-09 09:15:07 +08:00

RISCVDeadRegisterDefinitions.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVFeatures.td

[RISCV] Mark Zacas as non-experimental (#109651)

2024-09-25 06:14:43 +01:00

RISCVFrameLowering.cpp

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

RISCVFrameLowering.h

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

RISCVGatherScatterLowering.cpp

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

RISCVGISel.td

[RISCV][GISEL] instruction-select vmclr (#110782)

2024-10-04 12:51:04 -04:00

RISCVIndirectBranchTracking.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCVInsertReadWriteCSR.cpp

…

RISCVInsertVSETVLI.cpp

[RISCV][NFC] Remove the unused RISCV_COALESCE_VSETVLI_NAME (#111536)

2024-10-08 19:53:34 +02:00

RISCVInsertWriteVXRM.cpp

…

RISCVInstrFormats.td

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)

2024-10-08 14:09:07 +01:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISEL] Legalize G_EXTRACT_SUBVECTOR (#109426)

2024-10-01 14:08:49 -04:00

RISCVInstrInfo.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVInstrInfo.h

[CodeGen] Add generic INIT_UNDEF pseudo (#106744)

2024-09-05 09:34:39 +02:00

RISCVInstrInfo.td

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)

2024-10-08 14:09:07 +01:00

RISCVInstrInfoA.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVInstrInfoC.td

[RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRAI64_HINT. (#112250)

2024-10-14 15:25:29 -07:00

RISCVInstrInfoD.td

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

RISCVInstrInfoF.td

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

RISCVInstrInfoM.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVInstrInfoSFB.td

…

RISCVInstrInfoV.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

2024-09-05 15:27:48 +08:00

RISCVInstrInfoVPseudos.td

[NFC] Fix typos in comments (#109765)

2024-09-24 11:19:56 +02:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Add explicit XLenVT cast to vector load/store patterns.

2024-09-23 16:02:58 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Lower vector_reverse for zvfhmin/zvfbfmin (#110218)

2024-10-02 14:25:15 +08:00

RISCVInstrInfoXCV.td

[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (#100684)

2024-10-01 11:22:02 +10:00

RISCVInstrInfoXSf.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

2024-09-05 15:27:48 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Use THShift_ri class instead of RVBShift_ri for TH_TST instruction. NFC

2024-10-05 11:52:10 -07:00

RISCVInstrInfoXVentana.td

[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)

2024-07-27 17:26:32 -07:00

RISCVInstrInfoXwch.td

…

RISCVInstrInfoZa.td

…

RISCVInstrInfoZalasr.td

…

RISCVInstrInfoZb.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZc.td

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

RISCVInstrInfoZcmop.td

…

RISCVInstrInfoZfa.td

[RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)

2024-10-06 19:27:18 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Remove RISCVISD::FP_ROUND_BF16.

2024-09-03 20:18:01 -07:00

RISCVInstrInfoZfh.td

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

RISCVInstrInfoZicbo.td

…

RISCVInstrInfoZicfiss.td

…

RISCVInstrInfoZicond.td

…

RISCVInstrInfoZimop.td

…

RISCVInstrInfoZk.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZvfbf.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

2024-09-05 15:27:48 +08:00

RISCVInstrInfoZvk.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

2024-09-05 15:27:48 +08:00

RISCVISelDAGToDAG.cpp

[RISCV][ISel] Select binvi for pattern icmp eq/ne X, pow2 (#110957)

2024-10-03 15:13:02 +08:00

RISCVISelDAGToDAG.h

[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284)

2024-09-11 21:13:26 -07:00

RISCVISelLowering.cpp

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

RISCVISelLowering.h

[TTI] NFC: Port TLI.shouldSinkOperands to TTI (#110564)

2024-10-09 14:30:09 -07:00

RISCVLandingPadSetup.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

…

RISCVMacroFusion.td

…

RISCVMakeCompressible.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVMergeBaseOffset.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVMoveMerger.cpp

…

RISCVOptWInstrs.cpp

[RISCV] Add some Zfinx instructions to hasAllNBitUsers.

2024-08-08 17:33:54 -07:00

RISCVPostRAExpandPseudoInsts.cpp

…

RISCVProcessors.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814)

2024-09-17 18:52:55 +03:00

RISCVProfiles.td

[RISCV] Use listconcat to shorten some of the profile feature lists. (#102356)

2024-08-08 09:15:43 -07:00

RISCVPushPopOptimizer.cpp

…

RISCVRedundantCopyElimination.cpp

…

RISCVRegisterInfo.cpp

[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)

2024-09-30 23:52:35 -07:00

RISCVRegisterInfo.h

[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)

2024-09-30 23:52:35 -07:00

RISCVRegisterInfo.td

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVSchedRocket.td

…

RISCVSchedSiFive7.td

[RISCV][SiFive7] Change Latency of VCIX to the default (#106497)

2024-09-05 13:01:29 -04:00

RISCVSchedSiFiveP400.td

[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)

2024-08-19 09:41:42 -04:00

RISCVSchedSiFiveP600.td

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVSchedSyntacoreSCR1.td

…

RISCVSchedSyntacoreSCR7.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814)

2024-09-17 18:52:55 +03:00

RISCVSchedSyntacoreSCR345.td

[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)

2024-08-14 11:42:31 +03:00

RISCVSchedule.td

…

RISCVScheduleV.td

[RISCV] Move VLDSX0Pred from RISCVSchedSiFive7.td to RISCVScheduleV.td. NFC (#106671)

2024-09-01 21:02:06 -07:00

RISCVScheduleXSf.td

…

RISCVScheduleZb.td

…

RISCVScheduleZvk.td

…

RISCVSchedXiangShanNanHu.td

…

RISCVSubtarget.cpp

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

2024-08-08 09:17:43 -07:00

RISCVSubtarget.h

[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)

2024-09-16 09:48:25 +02:00

RISCVSystemOperands.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

2024-08-21 19:23:07 -07:00

RISCVTargetMachine.cpp

[RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244)

2024-10-14 20:54:17 +01:00

RISCVTargetMachine.h

…

RISCVTargetObjectFile.cpp

[RISCV] Support the large code model. (#70308)

2024-09-09 09:15:07 +08:00

RISCVTargetObjectFile.h

[Driver] Default -msmall-data-limit= to 0 and clean up code

2024-08-19 18:20:02 -07:00

RISCVTargetTransformInfo.cpp

[TTI] NFC: Port TLI.shouldSinkOperands to TTI (#110564)

2024-10-09 14:30:09 -07:00

RISCVTargetTransformInfo.h

[SLP]Initial support for interleaved loads

2024-10-14 09:12:33 -04:00

RISCVVectorPeephole.cpp

[RISCV] Check vmerge's true is in same block in vmerge -> vmv.v.v peephole (#110861)

2024-10-03 12:02:54 +08:00

RISCVVLOptimizer.cpp

[RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244)

2024-10-14 20:54:17 +01:00

RISCVZacasABIFix.cpp

[RISCV] Add additional fence for amocas when required by recent ABI change (#101023)

2024-09-19 13:39:56 +01:00