Luke Lau db57fc4edc [RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244) ...

If a pseudo has a passthru, I believe the first source operand will have
operand no 2, not 1.

2024-10-14 20:54:17 +01:00

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AArch64

Revert "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112200)

2024-10-14 21:43:49 +08:00

AMDGPU

[AMDGPU] Skip terminators when forcing emit zero flag (#112116)

2024-10-14 11:46:18 -04:00

ARC

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ARM

[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU (#110085)

2024-10-14 15:48:12 +01:00

AVR

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BPF

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CSKY

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DirectX

[HLSL] Implement the degrees intrinsic (#111209)

2024-10-10 16:34:26 -07:00

Generic

[test] Fix llc-start-stop.ll when the default target enables the loop terminator folding pass

2024-10-07 16:06:44 +01:00

Hexagon

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Inputs

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Lanai

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LoongArch

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M68k

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Mips

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MIR

[MIR] Fix tests for flags in register info (#112179)

2024-10-14 18:28:54 +05:30

MLRegAlloc

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MSP430

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NVPTX

[NVTPX] Copy kernel arguments as byte array (#110356)

2024-10-14 12:12:27 -07:00

PowerPC

[MIR] Fix tests for flags in register info (#112179)

2024-10-14 18:28:54 +05:30

RISCV

[RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244)

2024-10-14 20:54:17 +01:00

SPARC

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SPIRV

[HLSL] Implement the degrees intrinsic (#111209)

2024-10-10 16:34:26 -07:00

SystemZ

[SystemZ] Remove inlining threshold multiplier. (#106058)

2024-10-07 10:59:45 +02:00

Thumb

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Thumb2

SelectionDAG/expandFMINNUM_FMAXNUM: skips vector if SETCC/VSELECT is not legal (#109570)

2024-10-10 08:39:25 +08:00

VE

[TargetLowering][SelectionDAG] Exploit nneg Flag in UINT_TO_FP (#108931)

2024-10-14 20:55:48 +04:00

WebAssembly

[Coverage][WebAssembly] Add initial support for WebAssembly/WASI (#111332)

2024-10-15 02:41:43 +09:00

WinCFGuard

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WinEH

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X86

[TargetLowering][SelectionDAG] Exploit nneg Flag in UINT_TO_FP (#108931)

2024-10-14 20:55:48 +04:00

XCore

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Xtensa

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