7b0c41841e
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15. This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146488
46 lines
1.6 KiB
LLVM
46 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
|
|
; RUN: -target-abi ilp32f < %s | FileCheck %s
|
|
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
|
|
; RUN: -target-abi lp64f < %s | FileCheck %s
|
|
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
|
|
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
|
|
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
|
|
; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
|
|
|
|
; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
|
|
define half @half_imm() nounwind {
|
|
; CHECK-LABEL: half_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
|
|
; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECKIZFHMIN-LABEL: half_imm:
|
|
; CHECKIZFHMIN: # %bb.0:
|
|
; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI0_0)
|
|
; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
|
|
; CHECKIZFHMIN-NEXT: ret
|
|
ret half 3.0
|
|
}
|
|
|
|
define half @half_imm_op(half %a) nounwind {
|
|
; CHECK-LABEL: half_imm_op:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
|
|
; CHECK-NEXT: flh fa5, %lo(.LCPI1_0)(a0)
|
|
; CHECK-NEXT: fadd.h fa0, fa0, fa5
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECKIZFHMIN-LABEL: half_imm_op:
|
|
; CHECKIZFHMIN: # %bb.0:
|
|
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
|
|
; CHECKIZFHMIN-NEXT: lui a0, 260096
|
|
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
|
|
; CHECKIZFHMIN-NEXT: fadd.s fa5, fa5, fa4
|
|
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; CHECKIZFHMIN-NEXT: ret
|
|
%1 = fadd half %a, 1.0
|
|
ret half %1
|
|
}
|