David Sherwood 2dd4167a09 [LoopVectorize][AArch64] Add limited support for scalable vectorisation of i1 types (#95920) ...

Previously isElementTypeLegalForScalableVector returned false for i1
types, which also prevented vectorisation of loops with i1 reductions.
This is overkill - we only need to disable vectorisation for loads
and/or stores of i1 types. I've added i1 as a legal type, but changed
the cost model to return an invalid cost for loads and stores.

2024-06-25 15:04:24 +01:00

..

AArch64

[LoopVectorize][AArch64] Add limited support for scalable vectorisation of i1 types (#95920)

2024-06-25 15:04:24 +01:00

AMDGPU

[AMDGPU] Vectorize more 16 bit shuffles (#90648)

2024-05-21 09:21:36 -07:00

ARM

[ARM] Armv8-R does not require fp64 or neon. (#88287)

2024-05-07 11:48:30 +01:00

PowerPC

[PowerPC] adjust cost for extract i64 from vector on P9 and above (#82963)

2024-03-04 09:37:11 +08:00

RISCV

[RISCV][CostModel] Remove cost of icmp inst in icmp+select with SFB. (#91158)

2024-05-20 16:03:18 +08:00

SystemZ

[SystemZ] Add custom handling of legal vectors with reduce-add. (#88495)

2024-04-12 18:05:30 +02:00

X86

[X86] Lower vXi8 multiplies using PMADDUBSW on SSSE3+ targets (#95690)

2024-06-25 12:25:56 +01:00

free-intrinsics-datalayout.ll

[CostModel] No cost for llvm.allow.{runtime,ubsan}.check() (#86064)

2024-03-31 22:27:57 -07:00

free-intrinsics-no_info.ll

[CostModel] No cost for llvm.allow.{runtime,ubsan}.check() (#86064)

2024-03-31 22:27:57 -07:00

no_info.ll

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